nmix-0016manual

NEW MICROS, INC.

1601 CHALK HILL RD.

DALLAS, TX. 75212

PH: 214 339-2204

FAX: 214 339-1585

http://www.newmicros.com

Email: nmitech@newmicros.com

NMIX-0016: SAB80C535 SINGLE BOARD COMPUTER (8051 CORE TYPE)

Rev. 1.4 : 071393

The NMIX-0016 board is a SAB80C535 based single board com-

puter that provides for the connection of a LCD Display Module

with up to 4 lines of 40 characters and a 20 key (4 x 5 Matrix)

Keyboard to the Seimens SAB80C535 Microcontroller. The board has

a versatile memory map configured into three memory sockets that

are selectable for type or size of memory device. The memory

configuration can be set-up in the following formats:

* 64K Byte Program/Data Space

* 32K Program, 32K Program/Data, and 32K Data Space

* 64K Program and 64K Data Space

The Seimens SAB80535 Microcontroller includes the following

features:

* 256 Bytes of Internal Ram

* 8 Bit 8 Channel Analog to Digital Converter with external

reference inputs.

* 6 Eight Bit I/O Ports ( 2 are used for address/data bus)

* 3 Powerful Sixteen Bit Counter/timers (1 maybe used for

Baud Rate)

* Full-duplex Serial Port

* Watchdog Timer

* Low Power and Power Down Modes

Other on board features:

* Active Voltage detector for Reset operation - 4.5V.

* VBB battery circuit for back-up of memory during power

down.

* RS-232 or RS422/485 level conversion of Serial Port.

* VSC-34 stacking connector for adding NMI periphials.

* 2 x 4 inch prototyping area.

Specifications:

100mm wide x 150mm long with prototype area and

mounting holes.

+5V Power input at 80ma typical.

TABLE OF CONTENTS:

GETTING STARTED ........................... 3

NMIX AND NMIT BOARD DIFFERENCES ........... 4

NMIX-0016 BOARD MEMORY .................... 4

Memory option straps ................. 5

Memory socket configuration .......... 6

Memory socket option straps .......... 7

VSC34 EXPANSION CONNECTOR (J1) ............ 8

J6 Interrupt option strap ............ 8

DC POWER, BATTERY BACK-UP, AND RESET ...... 9

SERIAL I/O ................................ 10

J47 RS422/485 option strap ........... 11

J41 Serial I/O Connector ............. 12

PARALLEL I/O .............................. 13

J2 Parrallel Port Connector .......... 13

KEYBOARD INTERFACE......................... 14

J9 Keyboard Connector ................ 14

LCD INTERFACE ............................ 15

J8 LCD Connector ..................... 15

SAB80535 RAM AND SPECIAL FUNCTION REGISTERS 16

Core Registers ...................... 16

Port Registers ...................... 17

Timer Registers ..................... 18

Serial I/O Registers ................ 21

Interrupt Registers ................. 22

Watchdog ............................ 25

A/D Converter Registers ............. 26

TROUBLESHOOTING .......................... 28

NMIX-0016 MEMORY MAP ..................... 30

Appendix A: LCD Program in Forth ......... 31

Keyboard Program in Forth .... 32

Appendix B: Intel Hex Dump in Forth ...... 33

ATTACHMENTS:

NMIX-0016 Schematic Diagram

NMIX-0016 PCB Board Print

GETTING STARTED

The NMIX-0016 is the single board computer when purchased in

development configuration, it is complete and ready to run. The

NMIT-0016 is a target version of the NMIX-0016. It is made from

the same printed circuit board as the NMIX-0016, but has fewer

parts installed. Normally, a developer will use the NMIX-0016

for development, and high end projects, then switch to the lower

cost NMIT-0016 (or a modified version of it - call NMI) when

volume buying begins.

To operate the NMIX-0016 system, plug in the wall transformer and

connect a terminal to the serial RS-232 DB25F connector. Most

terminals should plug in directly, with a straight through cable

(ie: pin 1 to pin 1, 2 to 2, 3 to 3, etc.). The NMIX-0016 uses

only lines 2 and 3 for serial in and serial out respectively, and

pins 1 and 7 for ground. Many terminals require additional hand-

shaking signals to work, so pins 4 and 5 are hooked together on

the DB25F connector, as are pins 6 and 20. In this way the ter-

minals that require the additional handshake signal have their

own " clear to send" / "ready to send" and "data terminal ready"

/ "data set ready" signals wrapped back around, indicating

"always ready".

In order to talk to the NMIX-0016 the terminal must have the cor-

rect bit settings. The baud rate should be set at 9600 baud for

the standard 11.59 Mhz crystal system. The NMIX-0016 sends and

receives a bit protocol of one start bit, eight data bits and one

stop bits.

+---+---+---+---+---+---+---+---+---+---+

| S | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | S |

+---+---+---+---+---+---+---+---+---+---+

When the terminal is set correctly, every time you depress and

release the reset button the NMIX-0016 should respond with:

Max-FORTH Vx.x ( Assuming you are using the Forth )

NMI 8051 MONITOR Vx.x ( Assuming you are using the monitor )

with help menu...

Seeing the message means the terminal can see the NMIX-0016.

Press "return" on your terminal several times. If the NMIX-0016

responds with "OK" (FORTH) or ">" (MONITOR) each time, communic-

tions are established.

Your NMIX-0016 is now running and communicating as it should.

NMIX AND NMIT DIFFERENCES:

The NMIT-0016, when purchased in the generic target configura-

tion, is a minimum, 5 Volt only, configuration. The SAB80C535,

crystal, reset circuit, various HC "glue" logic components and

three 28 pin JEDEC memory sockets. Typically, a program

developed in the "development configured" board will be installed

in the "generic target configured" board for production of a dedi-

cated application. The user must install the appropriate

jumpers, which are not provided in the target configuration.

All configurations of the SAB80C535 based NMIX-0016 boards use

the same base PC board. Configuration differences refer to the

extent to which the board is filled with components.

NMIX-0016 MEMORY

The memory map allows up to a full 64K Bytes of Program

memory and 64K Bytes of Data memory. The U2 and U3 memory sockets

can be configured as combined Program and Data Memory creating a

single 64K Byte block of usable memory space. In this mode, U4

cannot be populated or a bus conflict will occur due to U2 and U4

being selected as data memory at the same time. Following are

the U2, U3, and U4 type of memory and address range combinations:

PROGRAM ONLY PROGRAM/DATA COMBINED DATA ONLY

U2 0000 - FFFF HEX 0000 - 7FFF HEX Not Avail.

U3 Not Avail. 8000 - FFFF HEX 8000 - FFFF HEX

U4 Not Avail. Not Avail. 0000 - 7FFF HEX

VSC Not Avail. 8000 - FFFF HEX 8000 - FFFF HEX

OPTION FOR ROM (80515) / ROMLESS (80535) TYPE PROCESSOR:

EXTERNAL / INTERNAL PROGRAM ROM ENABLE

J7: ROM (80515) OR ROMLESS (80535) OPERATION

+---------+

| XXXX o | ROMLESS OPERATION (* DEFAULT)

+---------+

| XXXX | ROM OPERATION (80515 ONLY)

+---------+

SPECIAL OPTION FOR BASIC USE:

ALE ENABLE / DISABLE FOR BASIC 52 OPERATION

J33: ALE NORMAL OR ALE BASIC 52 CONTROLLED

+---------+

| XXXX o | ALE OPERATES NORMALLY

+---------+

| o XXXX | ALE BASIC 52 CONTROLLED

+---------+

MEMORY CONFIGURATION OPTION STRAPPING J4, J5, J31, AND J32:

U2 PROGRAM MEMORY OPTIONS (BASE ADDRESS = 0000 HEX)

J4: PROGRAM ONLY / PROGRAM + DATA MEMORY

+---------+

| XXXX o | U2 = PROGRAM ONLY

+---------+

| o XXXX | U2 = PROGRAM + DATA (U4 NOT INSTALLED!)

+---------+

J5: 32K / 64K PROGRAM MEMORY SIZE

+---------+

| XXXX o | U2 = 64K PROGRAM (J4 = PROGRAM ONLY!)

+---------+

| o XXXX | U2 = 32K PROGRAM or PROGRAM + DATA

+---------+

U3 MEMORY TYPE OPTIONS (BASE ADDRESS = 8000 HEX)

J31: PROGRAM + DATA / DATA ONLY

+---------+

| XXXX o | U3 = 32K PROGRAM + DATA (J5 = 32K)

+---------+

| o XXXX | U3 = 32K DATA ONLY

+---------+

VSC34 (J1) CONNECTOR, MEMORY TYPE SELECTION

J32: VSC34 = U2 OR U3 MEMORY TYPE

+---------+

| XXXX o | VSC34 = J4 SELECTION

+---------+

| o XXXX | VSC34 = J31 SELECTION

+---------+

MEMORY DEVICE SOCKET ORGANIZATION AND OPTION STRAPPING:

Jumper Assignments for JEDEC 28 Pin Sockets

+---+

JUMPER 1 o o 28 +5 | o |

| | *

A12 2 o o 27 JUMPER | o |

+---+

A7 3 o o 26 JUMPER

A6 4 o o 25 A8

A5 5 o o 24 A9

A4 6 o o 23 A11

A3 7 o o 22 OE

A2 8 o o 21 A10

___________

A1 9 o o 20 CHIP SELECT

A0 10 o o 19 D7

D0 11 o o 18 D6

D1 12 o o 17 D5

D2 13 o o 16 D4

GND 14 o o 15 D3

PIN 1 PIN 26 PIN 27

O---O O---O O---O

O O O O O O

A14 +5 +5 A13 A14 RR/W

* Option of pullups on R/W lines to write protect RAMs in

socket. To use, install 100K pullup resistor & remove jumper

for pin 27. If battery backup is in use, RAM will then emulate

ROM.

MEMORY DEVICE SOCKET JUMPER SETTINGS

GENERAL PURPOSE SOCKET - U6, U7, U8

Jumper Settings for Standard JEDEC 24/28 Pin Devices

ALL 8K X 8 DEVICES

2764, 2864, 6264

PIN 1 PIN 26 PIN 27

+---+---+---+---+---+---+

| | X | X | | | X |

+---+---+---+---+---+---+

A14 +5V +5V A13 A14 RR/W

16K X 8 EPROM

27128

PIN 1 PIN 26 PIN 27

+---+---+---+---+---+---+

| | X | | X | | X |

+---+---+---+---+---+---+

A14 +5V +5V A13 A14 RR/W

32K X 8 EPROM

27256

PIN 1 PIN 26 PIN 27

+---+---+---+---+---+---+

| | X | | X | X | |

+---+---+---+---+---+---+

A14 +5V +5V A13 A14 RR/W

32K X 8 RAM

62256

PIN 1 PIN 26 PIN 27

+---+---+---+---+---+---+

| X | | | X | | X |

+---+---+---+---+---+---+

A14 +5V +5V A13 A14 RR/W

NOTE: All sockets are memory mapped as 32K memory space. When

a smaller device than 32K is placed in the socket, the contents

of the device will be mirrored through out the 32K memory space.

For instance the contents of an 8K device will appear 4 consec-

tive times on 2000 hex address boundaries.

J1 VSC34 BUS EXPANSION CONNECTOR

The J1 expansion connector was designed to follow the JEDEC stan-

dard for byte sized memory parts in the 8, 16 and 32K Byte

varieties. This connector allows for the easy addition of

periphial boards that can be placed anywhere in the memory map.

NMI offers an extensive line of I/O, A/D, D/A, and other

periphials.

VSC34 EXPANSION JACK J1

MEMDIS o o N.C.

E o o RST

A15 o o INT

A14 o o +5

A12 o o R/W

A7 o o A13

A6 o o A8

A5 o o A9

A4 o o A11

A3 o o OE

A2 o o A10

A1 o o AS

A0 o o D7

D0 o o D6

D1 o o D5

D2 o o D4

GND o o D3

VSC34 (J1) CONNECTOR INTERRUPT SELECTION

J6: J1 VSC34 INT'= INT0' OR INT1'

(Note: Remove for no Interrupt)

+---------+

| XXXX o | J1 VSC34 INT'= INT0'

+---------+

| o XXXX | J1 VSC34 INT'= INT1'

+---------+

DC POWER, BATTERY BACK UP, AND RESET

Connection TB1 provides a means to connect an external +5VDC

power source and Ground. The other connection on TB1 provides

access to for VBB battery voltage input.

The battery backup capability allows data retention in otherwise

volitale CMOS RAMs and the processor's own internal RAM through

main-board power-downs. A third terminal on the power connector,

TB1, is marked VBB for Voltage Battery Backup.

The VBB terminal on TB1 is connected to the VBB supply rail on

the board by diode, D1. The VBB supply rail supplied the three

28 pin JEDEC sockets, the 8054HN low voltage indicator in the

reset circuit (Rev A), and one 74HC00 gate. If no power is ap-

plied to the VBB terminal, the VBB rail is supplied through a P

channel FET, Q1, to within a diode drop of the suppling 5 volt

rail (~4.4 Volts). When the 8054HN low voltage indicator

releases the reset line, Q1 is turned on and the VBB comes almost

completely up to the 5 volt rail (~4.95 Volts). (This may cause

some problem with the Dallas Semiconductor DS1223 battery sock-

ets, as they "write protect" their RAMs at 4.75 Volts. Running

an elevated 5 Volt supply may be necessary to accomodate these

parts. The purpose of this feature is, however, to do away with

the need for those devices in final system configurations.)

When the 8054HN low voltage indicator holds the reset line low

(when VBB is below 3.8-4.2 Volts, Rev A), Q1 is turned off and

the address decoder is disabled through the same input that is

used by MEMDIS. This "access" protects the memories during the

power down cycle.

To meet the full letter of the specifications of the parts in-

volved the correct backup voltage on the VBB pin is critical.

This supply must be low enough to ensure that after the diode

drop of D1, the VBB rail cause the 8054HN to issue a reset (~4.0

Volts), otherwise Q1 will remain on and the whole system will be

the diode drop of D1, the VBB rail will meet the processors re-

quired backup voltage (listed as 3.3 Volts). Therefore, the

ideal voltage for the VBB supply is 3.9 - 4.5 Volts. It should

be pointed out, however, the Seimens specification appears to be

overly conservative. By empirical test, VBB supplies below 3

Volts appear to be quite adequate. Most CMOS RAMs will retain

data down to 2.2 Volts. Accounting for the diode drop under such

low currents, the VBB supply may work as low as 2.5 Volts.

SERIAL I/O

The SAB80C535 has a full duplex hardware serial channel that

operates at CMOS levels. To use this serial channel with most

standard communications interfaces, level converters are needed.

Drivers for RS-232C and RS-422/485 drivers are on the board. (It

should be noted that only one combination of RS-232 driver, RS-

422 drivers or RS-485 driver should be used at one time to avoid

contention of their receiver outputs.)

A zero by RS-232C specification is any voltage from +3 to +15

Volts, a one is between -3 and -15 Volts. To convert the HC sig-

nals to the voltage ranges of that interface standard, the NMIX-

0016 uses a single 16 pin device, the ICL232.

The ICL232 is ideally suited for this use. It not only provides

an RS-232 receiver and transmitter pair for the SAB80C535 proces-

sor, but also a spare RS-232 receiver and transmitter pair which

can be used with port lines for handshaking or software driven

UARTS, etc.. It also generates the higher voltages needed for

full RS-232 communications standards by way of an internal charge

pump. This allows output swings of a nominal + and - 9V, even

though the chip is only supplied +5V. (The negative output is

also used to get the negative voltage bias for the display to in-

crease contrast.)

The RS-422 standard represents a newer interface now coming into

popularity, and with good reason. Unlike the RS-232 requirements

which specify a single wire voltage transmission referenced to

ground, the RS-422 standard uses a voltage differential on a pair

of conductors. While the RS-232 at full volatge drive levels in

electrically noisy environments is barely reliable at distances

to 1000 feet, RS-422 signals are considered reliable at distances

up to 4000 feet. The RS-422 drivers operate, requiring only a

single sided 5 Volt supply, over twisted pairs of wires. A full

duplex connection for RS-422 requires two twisted pairs, one for

transmit, one for recieve. The shield of the twisted pair should

act as the common return path for the signals.

continued on next page....

The RS-485 interface uses the same specifications for its trans-

mitters and receivers. It, however, allows a single twisted pair

to be used for incoming and outgoing messages. This is ac-

complished by having both a transmitter (with 3 state ability)

and a reciever tied in parallel to the same twisted pair. Mul-

tiple drop point communications are possible under this scheme

(up to 64 pairs by specification). Of course, in application the

transmitter turns on and takes control of the lines only under

software control. The actual implemmentation of this control

will be determined by the particular protocol being used in the

communication network. Usually one master sends an addresses mes-

sage to one of multiple slaves and then turns off its master

transmitter. The addressed slave, recognizing its address will

turn on its transmitter and respond with the requested data.

These two interfaces are accomodated on the NMIX-0016 by the addi-

tion of two 8 pin 75176's, which each contain a

transmitter/receiver pair. Whether the transmitter of the pair

is active, or not, is controlled by a signal on one of its pins.

One of the 75176's (U9) has its receiver always enabled. It is

used exclusively as the RS-422 receiver. The other 75176 (U8)

can be used as the RS-422 transmitter if jumper J47 on the NMIX-

0016 is grounded (ie: in 422 position), or it can be used as the

receiver and transmitter for the RS-485 interface as controlled

by Port 4 pin P4.7 (ie: in 485 position). In this case if P4.7

is low, the 75176's transmitter is not active. If P4.7 is high

its transmitter is active. Following is the option strapping:

J47: 485 / 422 OPTION SELECTION

+---------+

| XXXX o | P4.7 CONTROLLED (485)

+---------+

| o XXXX | TRANSMIT ENABLED (422)

+---------+

SERIAL INPUT/OUTPUT JACK J41

TOP VIEW

NUMBERED LEFT TO RIGHT

1 2 3 4 5 6 7 8 9 10 11 12 13 14

----------------------------------------

o o o o o o o o o o o o o o

DB25F J41 Signal Name

----- --- -----------------------------

1 RS-422 Receive - Differential output

2 RS-422 Receive + Differential output

3 RS-422 Receive - Differential input or 485 xcv

4 RS-422 Receive + Differential input or 485 xcv

1 5 Case ground

2 6 Serial into NMIX-0020 (RXD)

3 7 Serial out of NMIX-0020 (TXD)

7 8 Electrical ground

9 +5V IN or OUT

10 Electrical ground

11 VBIN ( Battery back-up supply)

12 Electrical ground

13 Reset line in or out

14 Electrical ground

Note that for a standard PC compatible connection with the DB25

connector, the hardware handshake lines should be NULLED. To do

this you can add the following jumpers on the DB25F connected to

the NMIX/T-0016:

Pin 4 (CTS) to Pin 5 (RTS)

Pin 20 (DTR) to Pin 6 (DTS)

PARALLEL PORTS:

The SAB80C535 has seven parallel ports, Port 0, 1, 2, 3, 4, 5,

and AIN. Two ports of the SAB80C535 are sacrificed to create a

64K address and data bus. Although some of the remaining port

lines have special multiplexed functions, they can all be used as

inputs or as outputs according to their individual designs. Some

of the port lines have direction registers allowing them to be

used as either inputs or outputs. The four remaining ports of

the SAB80C535 are brought out to connector J2. Power (+5V) and

ground are also available on J2.

INPUT/OUTPUT JACK J2

TOP VIEW

FRONT (EDGE) OF CARD v

| GND o o +5

| X P50 o o P51 X

| X P52 o o P53 X

| X P54 o o P55 X

| X P56 o o P57 X

| X P40 o o P41 X

| X P42 o o P43 X

34 pin header | X P44 o o P45 X

group | X P46 o o P47 X

| I AN0 o o AN1 I

| I AN2 o o AN3 I

| I AN4 o o AN5 I

| I AN6 o o AN7 I

| X P10 o o P11 X

| X P12 o o P13 X

| X P14 o o P15 X

| X P16 o o P17 X

I=INPUT O=OUTPUT X=EITHER

The lines can be used as individual inputs or outputs or in com-

bination. There are very few applications, however, where pins

are switched dynamically, sometimes used as inputs, sometimes as

outputs.

A voltage of 7/10 Vcc or greater will always be recognized as a

logical one. Voltages 2/10 Vcc or lower will always be regonized

as logic 0. Voltages applied above Vcc or below 0 Volts can

damage the computer.

Continued on next page...

The outputs of the SAB80C535 can sink 1.6 mA to ground while let-

ting the pin go no higher than 0.4 Volts for a "zero" and source

about .08 mA at 2.5 Volts for a "one". In terms of control, this

is a very small signal. Most relays require over 50 times more

current to operate. LED's typically take 5 mA to be visible. HC

levels are such that the output is sufficient to drive the input

on one pin of one TTL device or about a dozen of the lower power

LSTTL inputs. The output is sufficient to drive VMOS FET's and

Darlingtons with an external pull up which can in turn control

several amps of current. Usually, however, a buffer will be

needed to do serious interfacing.

KEYBOARD

The NMIX-0016 has a built-in Keypad Controller, the 74C923. This

device scans matrixes of keys up to 4x5 without processor inter-

vention. The keyboard controller U12 (74C923) is connected to

Port 4 Bits 0 to 4 and Port 1 Bit 0 of U1 (80535 MCU). Access to

the MCU ports is by direct addessing mode to the Special Function

Registers located in data memory between 80 and FF hex. Port 0

Bit 0 will be a high level when valid keyboard data is available

on Port 4 Bits 0 - 4. The keyboard data is represented as a bi-

nary number for the switch position that is active (closed) in

the 20 position key matrix. U12 provides debounce timing and mul-

tiple key down lock out to prevent erroneous key data. Appendix

A has a program example for useing the keyboard interface.

Connector J9 provides the keyboard connection. Compatible

keyboards are common and should be a simular to Grayhill Series

86 or 88 keyboards. Following is the pinout of J9:

KEYBOARD INPUT/OUTPUT JACK J9

TOP VIEW

NUMBERED LEFT TO RIGHT

1 2 3 4 5 6 7 8 9

--------------------------

o o o o o o o o o

C C R R C R R C C

O O O O O O O O O

L L W W L W W L L

1 2 3 2 3 1 4 4 5

LCD INTERFACE

The NMIX-0016 has a built-in connector (J8) and decode circuitry

to allow direct interfacing to many of the popularly available,

intelligent LCD displays. A wide number of LCD modules can be

accommodated, since many manufacturers make the modules with the

same controller chips or control operation. Some of these manufac-

turers are AND, Densitron, Epson, Optrex, Sharp, and Sieko. They

come in configurations such as 1x8, 1x16, 2x16, 1x20, 2x20, etc.,

up to 4x40 or 2x80.

Connector J8 contains 16 pins but will accept the 14 pin or 16

pin ribbon connectors from the standard LCD modules as the pin

out is common except for an addtional enable signal for the

larger displays. J1 is configured to accept ribbon connectors

that are taken off the back side of the LCD to allow flush mount-

ing of the module's display face to a front panel. Ribbon cables

attached this way have their signals mirrored.

The LCD interface is hard addressed at four consecutive loca-

tions, $FFE0 hex thru $FFE3 hex. On board logic provides the

necessary chip select and timing information to operate the dis-

plays. Address line A0 goes directly to the displays, so each

chip select represents two memory locations. The smaller dis-

plays, with up to 80 characters, use only one display controller

chip. Those with a larger number of characters use additional

display controller chips. Those with 16 pin connectors have up

to two controllers built-in.

The type display attached will determine its own access speed.

The board provides little support to the display processor, other

than providing the necessary signals, voltages, and gated chip

selects at the 80535 bus speed. The handling of the displays fol-

lows the manufacturer's specifications for the particular dis-

play. Example program segments are shown in Appendix A for

single controller, 2 line displays. For other configurations and

types refer to the manufacturer's literature.

LCD DISPLAY JACK J8

TOP VIEW

Pin 2 +5 o o GND Pin 1

Pin 4 A0 o o Vo Pin 3

Pin 6 E1 o o R/W' Pin 5

16 pin header Pin 8 D1 o o D0 Pin 7

group Pin 10 D3 o o D2 Pin 9

Pin 12 D5 o o D4 Pin 11

Pin 14 D7 o o D6 Pin 13

Pin 16 E2 o o Pin 15

SAB 80535 INTERNAL RAM AND REGISTER AREA MEMORY MAP.

The 80535 microcontroller contains 256 bytes of RAM and 128

bytes of Special Function Register area internally. Both the top

128 bytes of ram and the register area exsist in the data memory

map between 80 Hex and 0FF Hex. To access these areas in-

dividually, the correct addressing mode must be used. Following

is the addressing mode chart for correct access:

RAM 0 - 7F HEX: DIRECT AND INDIRECT MODES

RAM 80 - FF HEX: INDIRECT MODE ONLY (via register pointer)

SFR 80 - FF HEX: DIRECT MODE ONLY (no register pointers)

SAB80535 SPECIAL FUNCTION REGISTERS.

Following is the description and operation of the Special

Function Registers grouped by function. Note that these

registers can be accessed by DIRECT ADRESSING MODE only.

ADDRESSING AND CORE OPERATION REGISTERS:

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

81 Hex SP STACK POINTER: Initialized to 07H on Reset.

Increment and store, read and decrement type.

82 Hex DPL DATA POINTER LOW: Low byte of special MOV

instruction data pointer.

83 Hex DPH DATA POINTER HIGH: High byte of special MOV

instruction data pointer.

D0 Hex PSW PROGRAM STATUS WORD REGISTER: Condition code

and status register.

BIT 0: P - Parity flag, set or cleared by bit

count in the Accumulator.

BIT 1: F1 - User flag 1

BIT 2: OV - Overflow flag

BIT 3: RS0 - Register Bank select 0

BIT 4: RS1 - Register Bank select 1

RS1/RS0 Working Register Bank Chart

0 0 = Bank 0: 00 - 07 Hex

0 1 = Bank 1: 08 - 0F Hex

1 0 = Bank 2: 10 - 17 Hex

1 1 = Bank 3: 18 - 1F Hex

BIT 5: F0 - User flag 0

BIT 6: AC - Aux Carry flag (BCD ops)

BIT 7: CY - Carry flag

ADDRESSING AND CORE OPERATION REGISTERS continued:

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

E0 Hex ACC ACCUMULATOR: Accessable by both Bit and Byte

maniplulation instructions.

F0 Hex B B REGISTER: Multiply / Divide instructions or

general purpose use.

I/O PORTS: Ports are byte and bit addressable. Special functions

of each port are noted. Notes for operation as

general purpose I/O Ports:

1. Write of a 0 to any bit position will provide

an active low output with 1.5ma drive current.

2. A write of an 1 to any bit postion will cause a

low current (~20ua) pull-up to be applied to

the port.

3. An 1 must be written to each respective port

pin before a Read of valid input data from that

port pin can be performed.

4. Ports 1 and 3 alternate functions require that

a 1 be loaded into the Port Data Register.

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

80 Hex P0 PORT 0 DATA REGISTER: not available for I/O use

due to operation as the low byte of

Address/Data Bus.

90 Hex P1 PORT 1 DATA REGISTER: Aux functions include

Interrupts and Timer support.

BIT 0: Interrupt 3 Input, Capture Input for

CRC, and Compare 0 Output.

BIT 1: Interrupt 4 Input, Capture Input for

CC1, and Compare 1 Output.

BIT 2: Interrupt 5 Input, Capture Input for

CC2, and Compare 2 Output.

BIT 3: Interrupt 6 Input, Capture Input for

CC3, and Compare 3 Output.

BIT 4: External Interrupt 2 Input

BIT 5: Timer 2 External Reload Trigger Input

BIT 6: System Clock Output

BIT 7: Timer 2 Count or Gate Input

A0 Hex P2 PORT 2 DATA REGISTER: Not available for I/O use

due to use as high Byte of Address Bus.

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

B0 Hex P3 PORT 3 DATA REGISTER: Aux functions support Serial

Port, Timers, Interrupts, and External Bus.

BIT 0: RxD, Serial Receive Data Input.

BIT 1: TxD, Serial Transmit Data Output.

BIT 2: INT0, External Interrupt 0 Input

BIT 3: INT1, External Interrupt 1 Input

BIT 4: T0, Timer 0 Timebase Input

BIT 5: T1, timer 1 Timebase Input

BIT 6: WR, External Bus Write Strobe.

BIT 7: RD, External Bus Read Strobe.

E8 Hex P4 PORT 4 DATA REGISTER: Standard I/O port.

F8 Hex P5 PORT 5 DATA REGISTER: Standard I/O port.

TIMER SYSTEM REGISTERS: Timer/Counters 0, 1, and 2 are multi-mode

programmable upcounting counters.

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

88 Hex TCON TIMER CONTROL REGISTER: Timer 0 and Timer 1

control and External Interrupt 0 and 1

control.

BIT 0: IT0, Interrupt 0 type control.

1 = Neg. Edge, 0 = Low level

BIT 1: IE0, Interrupt 0 Edge Flag

BIT 2: IT1, Interrupt 1 type control.

1 = Neg. Edge, 0 = Low level

BIT 3: IE1, Interrupt 1 Edge Flag

BIT 4: TR0, Timer 0 enable.

BIT 5: TF0, Timer 0 Overflow Flag

BIT 6: TR1, Timer 1 enable

BIT 7: TF1, Timer 1 Overflow Flag

89 Hex TMOD TIMER MODE REGISTER: Timer 0 and Timer 1

Operating Mode Control.

Timer 0 uses bits 0 - 3.

BIT 0: M0, Mode bit (Refer to chart)

BIT 1: M1, Mode bit (Refer to chart)

BIT 2: C/T', Counter or timer select bit.

0 = Timer, 1 = Counter (P3 T0 pin)

BIT 3: GATE, Timer counter enabled by P3 INT0

pin high level.

TIMER SYSTEM REGISTERS continued:

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

89 Hex TMOD TIMER MODE REGISTER continued:

T0: MO / M1 CHART

0 0 8 bit Timer / Counter, TL0 = 5 bit

prescaler.

0 1 16 bit Timer / Counter

1 0 8 bit Auto-Reload Timer / Counter,

TH0 holds the reload value.

1 1 TH0 = 8 bit Timer / Counter

(T0 control)

TL0 = 8 bit Timer / Counter

(T1 control)

Timer 1 uses bits 4 - 7.

BIT 4: M0, Mode bit (Refer to chart)

BIT 5: M1, Mode bit (Refer to chart)

BIT 6: C/T', Counter or timer select bit.

0 = Timer, 1 = Counter (P3 T1 pin)

BIT 7: GATE, Timer counter enabled by P3 INT1

pin high level.

T1 MO / M1 CHART

0 0 8 bit Timer / Counter, TL1 = 5 bit

prescaler.

0 1 16 bit Timer / Counter

1 0 8 bit Auto-Reload Timer / Counter,

TH1 holds the reload value.

1 1 Timer 1 Disabled

8A Hex TL0 TIMER 0 LOW BYTE

8B Hex TL1 TIMER 1 LOW BYTE

8C Hex TH0 TIMER 0 HIGH BYTE

8D Hex TH1 TIMER 1 HIGH BYTE

C1 Hex CCEN COMPARE/CAPTURE ENABLE REGISTER: Compare /

capture enable and configuration for

CRC, CC1, CC2, and CC3.

BIT 1, 0: CRC REGISTER

OPERATION

0 0: Compare / Capture CC0 disabled

0 1: Capture on Edge @ P1.0/INT3/CC0

1 0: Compare enabled

1 1: Capture on write to CRCL

TIMER SYSTEM REGISTERS continued:

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

C1 Hex CCEN COMPARE/CAPTURE ENABLE REGISTER continued:

BIT 3, 2: CC REGISTER 1 Control

OPERATION

0 0: Compare / Capture CC1 disabled

0 1: Capture on Edge @ P1.1/INT4/CC1

1 0: Compare enabled

1 1: Capture on write to CCL1

BIT 5, 4: CC REGISTER 2 Control

OPERATION

0 0: Compare / Capture CC2 disabled

0 1: Capture on Edge @ P1.2/INT5/CC2

1 0: Compare enabled

1 1: Capture on write to CCL2

BIT 7, 6: CC REGISTER 3 Control

OPERATION

0 0: Compare / Capture CC3 disabled

0 1: Capture on Edge @ P1.3/INT6/CC3

1 0: Compare enabled

1 1: Capture on write to CCL3

C2 Hex CCL1 COMPARE/CAPTURE REGISTER 1 LOW BYTE

C3 Hex CCH1 COMPARE/CAPTURE REGISTER 1 HIGH BYTE

C4 Hex CCL2 COMPARE/CAPTURE REGISTER 2 LOW BYTE

C5 Hex CCH2 COMPARE/CAPTURE REGISTER 2 HIGH BYTE

C6 Hex CCL3 COMPARE/CAPTURE REGISTER 3 LOW BYTE

C7 Hex CCH3 COMPARE/CAPTURE REGISTER 3 HIGH BYTE

C8 Hex T2CON TIMER 2 CONTROL REGISTER: Timer 2 mode

control register.

BIT 0: T2I0, Timer 2 input select bit 0

BIT 1: T2I1, Timer 2 input select bit 1

OPERATION

0 0: No input selected, T2 stopped

0 1: Timer on, Clock= T2PS setting

1 0: Counter on, clock = P1.7/T2

1 1: Gated Timer, Gate = p1.7/T2

BIT 2: T2CM, Compare mode 0 / 1, clear / set

TIMER SYSTEM REGISTERS continued:

Address Sym. Definition and Bit Map

------- ---- --------------------------------------------

C8 Hex T2CON TIMER 2 CONTROL REGISTER continued:

BIT 3: T2R0, Timer Reload Mode bit 0

BIT 4: T2R1, Timer Reload Mode bit 1

OPERATION

0 0: Reload disabled

0 1: Reload Disabled

1 0: Auto-reload on T2 overflow

1 1: Reload on neg. edge P1.5/T2EX

BIT 5: I2FR, P1.4/INT2 edge, 0=neg., 1=pos.

BIT 6: I3FR, P1.0/INT3 edge, 0=neg., 1=pos.

BIT 7: T2PS, Prescaler Select, 0 = Fosc/12

1 = Fosc/24

Note: must = 0 in count mode.

CA Hex CRCL COMPARE/RELOAD/CAPTURE REGISTER LOW BYTE

CB Hex CRCH COMPARE/RELOAD/CAPTURE REGISTER HIGH BYTE

CC Hex TL2 TIMER 2 LOW BYTE

CD Hex TH2 TIMER 2 HIGH BYTE

SERIAL PORT REGISTERS: The serial port can operate in one of 4

modes. In all modes the serial data is transmitted from

RXD/P3.1 LSB first and recieved in RXD/P3.0. Following are

brief descriptions of each mode:

MODE 0: 8 bit shift register operation. Baud rate is fixed

at Fosc/12.

MODE 1: 10 bit operation, 1 start, 8 data, and 1 stop. Baud

rate can be selected from Timer 1 overflow rate

or internal baud rate generator.

MODE 2: 11 bit operation, 1 start, 8 data, 1 Programmable

(TB8/RB8) bit, and stop. Baud rate is selectable

between Fosc/32 or Fosc/64.

MODE 3: 11 bit operation, 1 start, 8 data, 1 Programmable

(TB8/RB8) bit, and stop. Baud rate can be

selected from Timer 1 overflow rate or internal

baud rate generator.

The internal baud rate register is fixed to Fosc/1250 or

Fosc/2500.

Timer 1 in auto-reload mode baud rate is (1/16 or 1/32) x

Fosc/(12 x (256 - TH1)).

SERIAL PORT REGISTERS continued:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

98 Hex SCON SERIAL PORT CONTROL REGISTER

BIT 7: SM0, Mode bit 0

BIT 6: SM1, Mode bit 1

OPERATION

0 0: Mode 0

0 1: Mode 1

1 0: Mode 2

1 1: Mode 3

BIT 5: SM2, Mode 0 = 0

Mode 1 = 1, then RI active with

Stop Bit.

Mode 2 = 1, then RI active on RB8

= 1.

Mode 3 = 1, then RI active on RB8

= 1.

BIT 4: REN, Reciever enable.

BIT 3: TB8, transmit 9th bit polarity.

BIT 2: RB8, received 9th bit polarity.

BIT 1: TI, transmit interrupt flag

BIT 0: RI, receive interrupt flag

99 Hex SBUF SERIAL PORT DATA BUFFER REGISTER: write to

transmit serial data, read to input

received serial data.

87 Hex PCON PERIPHIAL CONTROL REGISTER: Special purpose

rate generator rate selection.

BIT 0 - 6: reserved, must be clear

BIT 7: SMOD, serial port baud rate prescaler.

0 = max rate, 1 = 1/2 rate

INTERRUPT REGISTERS:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

A8 Hex IENO INTERRUPT ENABLE REGISTER 0:

BIT 0: EX0, External Interrupt 0 enable

BIT 1: ET0, Timer 0 Overflow Interrupt enable

BIT 2: EX1, External Interrupt 1 enable

BIT 3: ET1, Timer 1 Overflow Interrupt enable

BIT 4: ES, Serial Port Interrupt enable

BIT 5: ET2, Timer 2 Overflow or Reload

Interrupt enable

INTERRUPT REGISTERS continued:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

A8 Hex IENO INTERRUPT ENABLE REGISTER 0 continued:

BIT 6: WDT, Watchdog Timer Reset Flag

See Watchdog operation note.

BIT 7: EAL, Global Interrupt Enable, must be

set for any interrupt to occur

B8 Hex IEN1 INTERRUPT ENABLE REGISTER 1

BIT 0: EADC, A/D Convert Interrupt enable

BIT 1: EX2, External Interrupt 2 enable

BIT 2: EX3, External Interrupt 3/CC0 enable

BIT 3: EX4, External Interrupt 4/CC1 enable

BIT 4: EX5, External Interrupt 5/CC2 enable

BIT 5: EX6, External Interrupt 6/CC3 enable

BIT 6: SWDT, Watchdog Timer Start/Reset

See Watchdog operation note.

BIT 7: EXEN2, Timer 2 External Reload

Interrupt (T2EX) enable

A9 Hex IP0 INTERRUPT PRIORITY REGISTER 0: Interrupt

Priority level programming register 0,

see chart below for programming.

BIT 0: IADC, A/D convert priority

BIT 1: IEX2, External Interrupt 2 priority

BIT 2: IEX3, External Interrupt 3 priority

BIT 3: IEX4, External Interrupt 4 priority

BIT 4: IEX5, External Interrupt 5 priority

BIT 5: IEX6, External Interrupt 6 priority

BIT 6: WDTS, Watchdog Timer Status flag, see

Watchdog operation note.

BIT 7: Reserved

B9 Hex IP1 INTERRUPT PRIORITY REGISTER 1: Interrupt

Priority level programming register 1,

see chart below for programming.

BIT 0: IE0, External Interrupt 0 priority

BIT 1: TF0, Timer 0 Interrupt priority

BIT 2: IE1, External Interrupt 1 priority

BIT 3: TF1, Timer 1 Interrupt priority

BIT 4: RI/TI, Serial port Interrupt priority

BIT 5: TF2/EXF2, Timer 2 Interrupt priority

BIT 6: Reserved

BIT 7: Reserved

INTERRUPT REGISTERS continued:

PRIORITY PROGRAMMING CHART: Note that registers IP0 and IP1

work as a selection pair. Bit 0 to bit 5 of each

for the interrupt sources. Following is the priority

chart:

IP1 Bit IP0 Bit Priority Level

0 0 0 = Lowest

0 1 1

1 0 2

1 1 3 = Highest

Following is the IP1 and IP0 Interrupt source pair by

bit position chart:

IP1 IP0

BIT 0: IADC IE0

BIT 1: IEX2 TF0

BIT 2: IEX3 IE1

BIT 3: IEX4 TF1

BIT 4: IEX5 RI/TI

BIT 5: IEX6 TF2/EXF2

Example priority programming:

IP1 = 00001100 binary

IP0 = 00010100 binary

Priority Level from Highest to Lowest:

IEX3 / IE1 = Highest

IEX4 / TF1

IEX5 / RI/TI

IADC / IE0 / IEX2 / TF0 / IEX6 / TF2/EXF2 = Lowest

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

C0 Hex IRCON INTERRUPT REQUEST CONTROL REGISTER: Flag

or time to service information. Bit

positions with '*' must be cleared by

software to clear current interrupt

request. All others are cleared

automatically by interrupt service

process.

* BIT 0: IADC, A/D conversion complete

BIT 1: IEX2, External Interrupt 2 edge

detected.

BIT 2: IEX3, External Interrupt 3 edge

detected or CC0 function occurred.

INTERRUPT REGISTERS continued:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

C0 Hex IRCON INTERRUPT REQUEST CONTROL REGISTER continued:

BIT 3: IEX4, External Interrupt 4 edge

detected or CC1 function occurred.

BIT 4: IEX5, External Interrupt 5 edge

detected or CC2 function occurred.

BIT 5: IEX6, External Interrupt 3 edge

detected or CC3 function occurred.

* BIT 6: TF2, Timer 2 Overflow Flag

* BIT 7: EXF2, External Timer 2 Reload Pin

negative edge detect flag

WATCHDOG TIMER OPERATION: The watchdog timer will provide a means

of adding operational security to the operation of the

microcomputer. Once enabled under software control, the

watchdog timer can only be disabled by hardware RESET. The

RESET initialization service can determine if the reset was

caused by the watchdog circuit by testing the WDTS (6) bit

in the IP0 (A9 hex) register. The watchdog timer will count

65532 machine instuction cycles (Fosc/12) before timeout and

causing a RESET. Following is the Watchdog timer operation

procedure:

1. Start the Watchdog by setting the SWDT bit (6) in the

IEN1 (B8) register.

2. Within 65532 cycles the Watchdog timer should be cleared

by setting the WDT bit (6) in the IEN0 (A8) register and

with the immediatly following instruction, set the SWDT

bit (6) in the IEN1 (B8) register.

3. Provide in the program for the step 2 service to be

performed regularly to prevent the watchdog timer from

timeout.

ANALOG TO DIGITAL CONVERTER REGISTERS:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

D8 Hex ADCON A/D CONVERTER CONTROL REGISTER: Analog to

digital converter Mode, Mux input,

Status register. Also contains the

Clockout and Internal Baud generator

control bits.

BIT 0: MX0, Mux control bit 0, see chart

BIT 1: MX1, Mux control bit 1, see chart

BIT 2: MX2, Mux control bit 2, see chart

MUX Control Bit selection chart:

MX2 MX1 MX0 Input Channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 AN4

1 0 1 AN5

1 1 0 AN6

1 1 1 AN7

BIT 3: ADM, Conversion mode select,

1 = continously convert,

0 = perform 1 conversion and stop.

BIT 4: BSY, Conversion in progress flag. set

BIT 5: Reserved, must = 0

BIT 6: CLK, Enable clock (Fosc/12) out on

P1.6

BIT 7: BD, Baud Rate Generator enable

D9 Hex ADDAT A/D CONVERTER DATA REGISTER: A/D converter

conversion result register. Contents

valid until the next conversion is

complete.

DA Hex DAPR D/A CONVERTER PROGRAM REGISTER: Conversion

start and internal reference programming

start or restart a conversion sequence.

The register is divided into two 4 bit

nibbles for programming the high and low

reference voltages to the converter.

The low nibble adjusts the low level or

refernce ground (Gr). The high nibble

adjusts the high level or reference

voltage (Vr). The following table

defines the nibble value to reference

adjustment:

ANALOG TO DIGITAL CONVERTER REGISTERS continued:

Address Sym Definition and Bit Map

------- ---- --------------------------------------------

DA Hex DAPR D/A CONVERTER PROGRAM REGISTER continued:

NIBBLE VALUE Vr (High) Gr (Low)

0 = VRH (+5V) = VRL (0)

1 --- N/A 0.3125

2 --- N/A 0.625

3 --- N/A 0.9375

4 1.25 1.25

5 1.5625 1.5625

6 1.875 1.875

7 2.1875 2.1875

8 2.50 2.50

9 2.8125 2.8125

A Hex 3.125 3.125

B Hex 3.4375 3.4375

C Hex 3.75 3.75

D Hex 4.0625 --- N/A

E Hex 4.375 --- N/A

F Hex 4.6875 --- N/A

Note: High and Low reference must be separated by at least 4

steps for correct A/D operation.

A/D OPERATION:

1. Configure ADCON register for Mode (single or continous)

and channel inputs.

2. Determine value of reference desired and write the value

into DAPR to start the conversion process.

3. Poll ADCON busy flag or enable A/D converter interrupt to

process data at the end of the current conversion.

4. Read ADDAT before the next conversion cycle is complete

if required.

5. Start the conversion again if necessary.

TROUBLESHOOTING

As always the first thing to do when troubleshooting is to check

the power and ground connections. An oscilliscope should be used

to check signals. If +5 Volts is present at terminal block and

the board is not operational, the next item to check is the oscil-

lator. Putting the scope on XTAL1 (Pin 40) should show a ~11 Mhz

sine wave running from about .5 Volt lows to 4.5 Volt peaks.

XTAL2 (pin 39) should have an identical signal, but of a much

smaller amplitude. If the sine waves are not present and there

is 5V present at the power pin Vcc (Pin 68), and ground at Vss

(Pin 38), then either the SAB80C535 or the crystal are bad and

require replacement. There is one exception. If the processor

has executed a STOP instruction, the oscillator will stop. When

the oscillator is functioning correctly the ALE signal (pin 50)

will be present. The ALE signal drives the timing for the exter-

nal address / data bus demultiplexing. This signal should transi-

tion nearly rail to rail, a 0.4V low and a 4.6V high are normal.

Less amplitude can indicate a board short or an excessive load on

the line external to the SAB80C535.

The serial channel should send a sign on message (Monitor or

Forth installed) if no autostart ROM interferes. If not, the

reset circuit could be bad, the serial converter could have

failed, or the SAB80C535 could be defective. With the reset line

grounded, (Pin 10) should be at ground. When released, the pin

should rise to 5 Volts. If the reset pin is working and still no

message is seen on the terminal, check P3.1, the serial output

line (Pin 22). When reset is exercised, this line should go from

normally high through a multitude of toggles back to a high

state. The periods of the toggle transitions are multiples of

approximately 100 microseconds. If this signal is not present,

the Rom memory, Sab80C535, or memory option strapping is suspect.

If the signal is present, check pin 7 of J41. It should normally

be at -V (-9 Volts nominally) and should toggle to +V (+9 Volts

nominally) at the same rate as the serial output line. If this

is happening and no message is seen, the RS-232 wiring or the ter-

minal is suspect. Check to see if J41 is connected to the DB25F

RS-232 connector as follows:

DB25F Signal Name

----- ------ ----

1 Case ground

2 Serial in (to NMIX-0016)

3 Serial out (from NMIX-0016)

7 Electrical ground

4 to 5 (PC hardware handshake nulled)

6 to 20 (PC hardware handshake nulled)

Check the voltages on pins 2 and 3. If pin 3 is very negative and

pin 2 is floating, both systems are trying to talk on the same

line. Pins 2 and 3 need to be swapped. Usually this is done

with a "null modem" inserted where the two systems connect.

If the -V/+V signal was not found at pin 3, the RS-232 converter

is not working. Check pin 2 of the ICL232 for +V and pin 6 of

the ICL232 for -V. If these signals are not present, the charge

pump of the ICL232 has failed. Pin 14 of the ICL232, the output,

should look the same as pin 7 of J41.

Check pin 6 of J41 which is the serial into the board from the

terminal. It should normally be at a negative voltage between -3

and -15 Volts. When a key is pressed on the terminal it should

pulse to positive voltages between +3 and +15 Volts. If it

doesn't, the terminal or the RS-232 wiring are suspect. The same

signals at inverted TTL levels, should also be at P3.0, which is

the serial input line of the processor (Pin 21).

The most common error in trying to use the NMIX-0016 is mis-

matched baud rates or bit settings. Verify that the terminal is

set for 9600 baud with one start bit, eigth data bits and one

stop bits, with no parity generated. If using Forth, be sure to

use CAPITALS. (Review this discussion in the Getting Started

section.)

MEMORY MAP

HEX HEX

----- PROGRAM MEMORY ----- DATA MEMORY

$FFFF +------------+ $FFFF +------------+

| | | LCD I/O |

| | $FFE0 |------------|

| | | |

| U2 OR U3 | | U2 OR U3 |

| MEMORY | | MEMORY |

| SPACE | | SPACE |

| | | |

| SEE OPTION | | SEE OPTION |

| STRAPPING | | STRAPPING |

| | | |

$8000 |------------| $8000 |------------|

| | | |

| | | U2 OR U4 |

| U2 MEMORY | | MEMORY |

| SPACE | | SPACE |

| | | |

| | | SEE OPTION |

| | | STRAPPING |

| | | |

| | $0100 |------------|------------|

| | | REGISTERS | RAM |

| | $0080 |------------|------------|

| | | INTERNAL |

| | | RAM |

$0000 |............| $0000 |............|

APPENDIX A: MAX FORTH PROGRAM SEGMENTS

COLD

HEX

8100 TIB ! ( MOVE INPUT BUFFER )

50 TIB 2+ ! ( SET BUFFER LENGTH )

8400 DP ! ( MOVE DICTIONARY POINTER )

( *********************************************************** )

( LCD DISPLAY ROUTINES )

( *********************************************************** )

: IS CONSTANT ;

FFE0 IS DSP-CMD

FFE1 IS DSP-DATA

: WAIT-NOT-BUSY BEGIN DSP-CMD C@ 80 AND 0= UNTIL ;

: CLEAR WAIT-NOT-BUSY 1 DSP-CMD C! ;

: HOME WAIT-NOT-BUSY 2 DSP-CMD C! ;

: CRLF WAIT-NOT-BUSY C0 DSP-CMD C! ;

: MOVE-CURSOR WAIT-NOT-BUSY 80 OR DSP-CMD C! ;

: RIGHT-UPPER-CORNER 27 MOVE-CURSOR ;

: CURSOR? WAIT-NOT-BUSY DSP-CMD C@ 7F AND ;

: DSP>L WAIT-NOT-BUSY 10 DSP-CMD C! ;

: DSP>R WAIT-NOT-BUSY 14 DSP-CMD C! ;

: DSP-EMIT WAIT-NOT-BUSY DSP-DATA C! ;

: DSP-TYPE

BEGIN

DUP 0= NOT

WHILE

1- SWAP DUP C@ DSP-EMIT 1+ SWAP

REPEAT

2DROP

;

: DSP-TEST

." TYPE ^C TO QUIT "

CLEAR

BEGIN

KEY DUP

DUP D = IF CRLF DROP ELSE

DUP 8 = IF DSP>L 20 DSP-EMIT DSP>L DROP ELSE

DUP 3 = NOT IF DSP-EMIT THEN

THEN

3 =

UNTIL

;

: DSP-SPACE BL DSP-EMIT ;

: DSP-SPACES 0 MAX BEGIN ?DUP WHILE 1- DSP-SPACE REPEAT ;

: DSP-ON

WAIT-NOT-BUSY

38 DSP-CMD C! ( GET ATTN

38 DSP-CMD C! ( SET 2 LINE DISP )

6 DSP-CMD C! ( CHARACTER ENTRY RIGHT )

E DSP-CMD C! ( DISPLAY CONTROL ON, CURSOR ON )

;

( ************************************************************* )

( KEYPAD ROUTINES )

( ************************************************************* )

C8 IS KEYPAD

: KP-?TERMINAL KEYPAD C@ 40 AND ;

: KP-KEY

BEGIN

DROP KEYPAD C@ DUP 80 AND

UNTIL

1F AND

0 KEYPAD C!

;

: KP-EXPECT

OVER + OVER

BEGIN

0 OVER !

KP-KEY

DUP 0D =

DROP SPACE 1

ELSE

DUP 7F =

DROP

3 PICK OVER U<

- DUP MIN

8 EMIT

THEN

ELSE

2DUP =

THEN

UNTIL

2DROP DROP

;

APPENDIX B: APPLICATION NOTE

INTEL FORMAT DUMP COMMAND

The following program allows a section of memory to be dumped out

the serial channel in the Intel hex format which is a standard

used by many of the commercially available PROM programmers.

This program should allow the use of such programmers to capture

programs and data in EPROMs, which are not supported for program-

ming by the NMIX-0020 directly.

HEX

VARIABLE CHKSUM

: CE DUP A < IF 30 ELSE 37 THEN + EMIT ; ( CONVERT AND EMIT )

: 2.R FF AND 10 /MOD CE CE ;

: 4.R 0 100 UM/MOD 2.R 2.R ;

: INTEL-DUMP ( addr count --- )

OVER + SWAP ( CONVERTS ADDR & COUNT TO UPPER, LOWER ADDR )

BEGIN

2DUP 20 + MIN ( MAKE NEXT LINE OF OUTPUT UP TO 32 BYTES LONG)

SWAP ( BRING UP START ADDRESS, MOVE DOWN END ADDRESS )

." :" ( BEGIN THE RECORD )

2DUP - ( FIND OUT # OF BYTES IN THIS RECORD )

DUP CHKSUM ! ( BEGIN CHKSUM COMPUTATION )

2.R ( PRINT # OF BYTES IN RECORD IN TWO DIGIT FIELD )

DUP 100 /MOD + CHKSUM +! ( ADD START ADDRESS TO CHKSUM )

DUP 4.R ( PRINT START ADDRESS IN FOUR DIGIT FIELD )

." 00" ( PRINT RECORD TYPE, NO NEED TO ADD TO CHKSUM )

>R DUP R> ( MAKE START STOP #S FOR DO LOOP )

I C@ 2.R ( PRINT HEX BYTE IN TWO DIGIT FIELD )

I C@ CHKSUM +! ( UPDATE CHKSUM )

LOOP

CHKSUM @ FF AND NEGATE 2.R ( PRINT CHKSUM NEG 2 DIGIT FIELD )

2DUP =

UNTIL ( KEEP GOING TILL LINE END IS = TO BLOCK END )

CR ." :00000001FF" CR ( TACK ON END RECORD )

2DROP

;

Program and application courtesy of Danny Barger, International

Computing Scale.