New Micros, Inc

1601 Chalk Hill Road

Dallas, TEXAS 75212

Phone (214) 339-2204

Fax (214) 339-1585

Email: nmitech@newmicros.com

http://www.newmicros.com

SHORT INTRODUCTION

The NMIX-0026, is an MC68HC16 based single board computer. When

purchased in development configuration, is complete and ready to

run. The support circuitry required is held to an absolute

minimum through the use of a PLD. A rectifier/regulator

section converts 7-18V A.C. (or D.C.) power from an optional

wall transformer to usable 5VDC. Screw terminals are provided to

accept an external 5VDC supply if preferred.

The processor is expanded, having a 2M maximum, (1M normally)

address space. Four memory sockets are available for use in this

memory space. Decode logic allows various combinations of parts.

From 8K, 16K, 32K, 64K, 128K, 256K and 512K, even 1024K devices

can be accommodated by jumper setting.

Normally, a developer will use the NMIX-0026 for development,

and high end projects, then switch to the lower cost NMIT-0026

(or a modified version of it) when volume buying begins. The

NMIT-0026 is a target version of the NMIX-0026. It is made from

the same printed circuit board as the NMIX-0026, but has fewer

parts installed.

The NMIT-0026, when purchased in the generic target

configuration, is a minimum, 5 Volt only, configuration. The

MC68HC16, crystal, reset circuit, PLD and four 32 pin JEDEC

sockets. Typically, a program developed in the "development

configured" board will be installed in the "generic target

configured" board for production. The user must install the

appropriate jumpers, which are not provided in the target

configuration. All configurations of the MC68HC16 based

NMIX-0026 boards use the same base PC board. Configuration

differences refer to the extent to which the board is filled

with components. Custom versions, varying between the fully

populated NMIX, and the minimally populated NMIT boards are

available from NMI. Call for current policy and pricing.

GETTING STARTED IN Max-FORTH

To operate the NMIX-0026 system, plug in the wall transformer

and connect a terminal to the serial RS-232 DB25F connector.

Most terminals should plug in directly, with a straight through

cable (i.e.: pin 1 to pin 1, 2 to 2, 3 to 3, etc.). The

NMIX-0026 uses lines 2 and 3 for serial in and serial out

respectively, and pins 1 and 7 for ground. Many terminals

require additional hand shaking signals to work, so pins 4 and 5

are hooked together on the DB25F connector, as are pins 6 and

20. In this way, terminals that require the additional

handshake signals have their own " clear to send" / "ready to

send" and "data terminal ready" / "data set ready" signals

wrapped back around, indicating "always ready".

In order to talk to the NMIX-0026 the terminal must have the

correct bit settings. The baud rate should be set at 9600 baud.

The NMIX-0026 sends and receives a bit protocol of one start

bit, eight data bits and one stop bit.

When the tterminal is set correctly, every time you depress and

release the reset button the NMIX-0026 should respond with:

Max-FORTH Vx.x

Seeing that message means the terminal can see the NMIX-0026.

Press "return" on your terminal several times. If the NMIX-0026

responds with "OK" each time, communications are established.

Now, you will want to see the system do something. Type WORDS

followed by a return. This will cause the system to list its

entire vocabulary, some 300 plus words. The listing can be

stopped at any time by pressing a key, like the space bar.

The NMIX-0026 provides external memory expansion. 1K RAM,

internal to the 68HC16 is mapped starting at location 0.

External ROM is also mappped starting at location 0 and is

overlapped by the 1K internal 68HC16 RAM. External RAM is also

mapped starting at location 0. In normal operation, the

external ROM (minus the 1K internal RAM) is copied to external

RAM prior to execution. In order for this scheme to work with

Forth, the dictionary pointer (DP) needs to be moved to the

start of external RAM which is not overlapped by external ROM.

In the case of two 8K X 8 ROMS (16k), the dictionary pointer

will need to be brought out to memory location $4000 with the

following Forth instruction: HEX 4000 DP !

A graphical representation of the physical memory partitioning

just discussed is shown below:

|CHIP INTERNAL|ROM EXTERNAL|RAM EXTERNAL|

0k +-------------+------------+------------+

| 1 K | | |

| RAM | | |

1k +-------------+------------+ |

| 2 times | |

| 8K X 8 | |

| = 16K | |

| | |

$4000 16k +-------------+------------+------------|

START OF USABLE RAM | |

| 2 times |

| 128K X 8 |

| = 256K |

| |

| |

| |

| |

$3FFFF 256k +--------------------------+------------+

Now try a simple program to exercise some of these words. Enter:

: TYPE-LETTERS 5B 41 DO I EMIT LOOP ;

TYPE-LETTERS

to which the machine will respond:

: TYPE-LETTERS 5B 41 DO I EMIT LOOP ; OK

TYPE-LETTERS ABCDEFGHIJKLMNOPQRSTUVWXYZOK

Now have a look at memory with the DUMP command. Type:

0000 80 DUMP

and examine the results (remember we put the machine in HEX).

Enter "WORDS" on the keyboard again and observe that the first

word displayed has become the word TYPE-LETTERS defined above.

Max-FORTH V1.3 provided with the NMIX-0026 includes words that

store, read, move and dump to any memory location on the 1meg

memory map. The most important of these are the following:

L! n Laddr --

Example of use : FFFF FF700. L!

This command takes the number FFFF and stores it into the memory

location starting at 0FF700.

L@ Laddr -- n

Example of use: FF700. L@

This command fetches one word of data at memory location 0FF700

and places that value onto the stack.

LC! b Laddr --

Example of use: FF FF700. LC!

This command takes the number FF and stores it into the memory

starting at 0FF700.

LC@ Laddr -- b

Example of use: FF700. LC@

This command fetches one byte of data at memory location 0FF700

and places that value onto the stack.

LCMOVE source-Laddr dest-Laddr n --

Example of use: FF600. FF700. FF LCMOVE

This example copies FF bytes of information starting at 'source-Laddr'

to 'dest-Laddr'.

LDUMP Laddr n --

Example of use: FF700. FF LDUMP

This example displays FF bytes of information starting at memory

location FF700.

In the above examples 'n' is a 16 bit number, 'b' is an 8 bit

number. The long address format

FF700. implies an offset and bank. For the example FF700, the

bank is taken as 000F, the offset is F700. The offset is stored

to the stack first, followed by the bank. Both the offset and

the bank are 16 bit numbers.

For more information on the Max-FORTH language, refer to the

Max-FORTH User's Manual, order number UM-MAX.

Max-FORTH IN A NUTSHELL

Max-FORTH closely follows the basic human methodology for

dealing with language. Learning a "human" language starts with

understanding a few simple word. (I.e.: YES, NO, STOP, GO,

etc.). Next, phrases are made from those words. The meanings of

phrases are named, and new words are born. Then, larger, more

complex concepts are built from these simple beginnings.

Complicated words are defined in terms of simpler words. Using

the basics, larger and larger concepts are built as vocabulary

grows. (E.g. from the few words given above, STOP GO STOP means

JERK.)

Suggesting the closeness of this linkage, the program segments

in Max-FORTH are called words and are kept in a structure,

called the dictionary. The dictionary is a linked list with all

known words in the language. Max-FORTH provides a starter set of

over 300 words. These are the basics, just enough to begin

describing a programming task comfortably. Each word has a very

precise meaning, not at all ambiguous. To learn Max-FORTH, a few

of these words must be understood. From these simple words, low

level phrases can be described. The phrases are given names.

Newly defined words can be used in more complex definitions by

their name. As the programming task progresses, the number of

known words grows. While the later words can be more complex,

they are generally easier to understand in terms of named

purpose, more like the natural language equivalent.

The last word added to the dictionary fully describes the

program to be run. It does so in terms of words already known,

which are further described by other, underlying words, etc. The

pyramiding structure of lower words can be followed backwards

until segments "understandable" by the CPU (i.e.: machine code)

are reached. Those machine-coded words were provided in the

basic word set already defined in Max-FORTH (The process of

descending, from compiled word-pointer, to the next compiled

word-pointer, until finding machine code, is called threading.)

A Max-FORTH programmer describes the programming problem by

adding new definitions (or words, for short) to the dictionary.

They are defined in terms of the words already built into the

language, which the machine knows how to translate. The new

words are added to the linked list. They become part of the

language, describing the problem in terms the computer

"understands". As words are added, the dictionary grows. Each

added word describes another part of the program more

succinctly. A word in Max-FORTH can be evoked by stating its

name interactively. When the program is finished the whole

program has one name. The program can be invoked by entering its

name.

To facilitate dedicated applications, a word can also be started

when the computer is reset. An autostarted word has a special

demarcation, a recognition pattern and a pointer left in memory,

which indicates to the Operating System it should be run.

Max-FORTH itself is autostarted in this manner, by the Operating

System, if no other autostarted word is found.

Most programs for dedicated applications, are endless loops. The

endless loop of the Max-FORTH development language is called

the Outer Interpreter. This structure initializes the system,

then, repeatedly accepts an input line, translates it, returns

for another line, etc.

The syntax of Max-FORTH is remarkable simple. The language is

practically free form. The syntax is simply stated: Everything

input to the Outer Interpreter is either a word or a number. If

the input is not a known word or translatable as a number, it is

an error. (The strings found meaningless are echoed back,

followed by a question-mark.) Words and numbers are delimited by

spaces.

It would be easy to be misled to believe there is more syntax

associated with the Outer Interpreter. There is not. Words

sometimes have actions in themselves which gives the appearance

of syntax. For instance, comments appear to have a syntax. They

start with a "(" and end with a ")". A casual reader of

Max-FORTH code will be happily able to read most listings, by

knowing the things between free standing "(" and ")"s are

comments. It is not an action of the language that renders them

as an uninterpreted string, but rather the action of the word

"(" which throws away the input stream until its matching ")" is

found. Thus, the Outer Interpreter only sees the "(", executes

it and continues on. The rest of the comment is bypassed as

surely as if it were never there.

The feel of syntax, then, comes not from the language

interpreter itself, but from the individual words as they are

translated. Knowing the specific action of the words is

important, then. The most important are the defining words that

allow compilation of new definitions. Using the provided words

correctly will allow the language to be extended. Words that

extend the language are called defining words.

Max-FORTH is both an interpreter and a compiler. This is

facilitated by the Outer Interpreter's two states:

Interpretation Mode and Compilation Mode. Instructions can be

entered to be run "on the fly". This immediate "translation and

execution" is done in the Interpretation Mode. In the

Compilation Mode, the Outer Interpreter "translates", but,

generally, does not "execute" the functions found. If the word

has no markings as a word to be executed immediately, the Outer

Interpreter defers execution by storing them as executable

tokens in memory.

The word that switches the Outer Interpreter from Interpretation

Mode to Compilation Mode is ":" (pronounced "colon"). The word

that switches it out of Compilation Mode is ";" (pronounced

semicolon). When a ":" is interpreted in the input stream, its

execution has several effects. The Outer Interpreter is switched

to Compilation Mode. Also, the input stream is searched for a

string for use as a name for a new definition. This string is

used to create a dictionary entry for the new word.

This dictionary entry is called a "head". Linkages are added to

the head to allow it to be found in memory. This head will be

used for comparison with the input stream by the Outer

Interpreter to tell if the new definition is being referenced in

the input stream. After changing the Outer Interpreter's state,

making the head, and doing some minor error checking, ":" starts

the code section of the new word by laying in a pointer to a

routine that can translate the two byte tokens. It then returns

control back to the Outer Interpreter. The input stream pointer

is moved past the string. The Outer Interpreter continues to

evaluate the input stream.

Words now found will not be immediately executed. They are

compiled as tokens into the code section, or "body", of the new

definition being formed. Most functions compile into one 16-bit

memory "word" (two bytes). This means compiled Max-FORTH code is

very compact. A pointer to the "code" of the word to be later

executed is compiled into the next available two-byte spot in

the dictionary. This pointer is called the compiled words

Code-Field Address. This is a lower level linkage than the

dictionary structure, which points to names. Here, the function

is referenced by a physical memory address.

This compilation process continues until the word ";" is

encountered. The word ";" is from a special class of words which

has a precedence flag set, telling the Outer Interpreter not to

defer execution, but to run the word whenever found. This allows

";" to run, turning off the Compilation Mode, finishing up the

definition, doing some error checking, and enabling the new

definition to be found as a new word in the language.

Functions set between a ":" and a "name-string" on the starting

end, with a ";" at the end, are compiled into new definitions.

After the word has been created, its function can be invoked by

including its "name-string" in the input stream with the Outer

Interpreter in Compilation Mode. If the outer Interpreter is in

Compilation Mode, i.e.: making a newer word, including a word's

name in the input stream will cause the previously defined

function to be added to a newer words definition. So begins the

pyramiding of words upon words until a whole program is

described by one word which references all other word

definitions required.

For more information on the Max-FORTH language, refer to the

Max-FORTH User's Manual, order number UM-MAX.

I/O PORTS

The signal lines for the MC68HC16's ports are brought out on

the 44 pins of J1. J12 provides access to control signals.

INPUT/OUTPUT JACKS J1

TOP VIEW

FRONT (EDGE) OF CARD v

- GND o o +5

| X OC1 o o OC2 X

| X OC3 o o OC4 X

| X IC1 o o IC2 X

| X IC3 o o IC4 X

| I RXD o o TXD X

| X PS0 o o PS1 X

44 pin header | X PS2 o o PS3 X

group | X MS1 o o MS0 X

| GND o o SCK X

| O PMS o o PCL I

| O PMA o o PA1 I

| X IR1 o o IR2 X

| X IR3 o o IR4 X

| X IR5 o o IR6 X

| GND o o IR7 X

| I AD0 o o AD1 I

| I AD2 o o AD3 I

| I AD4 o o AD5 I

| I AD6 o o AD7 I

| VRLP o o VRHP

- GND o o RST

I=INPUT O=OUTPUT X=EITHER

The lines can be used as individual inputs or outputs or in

combination. There are very few applications, however, where

pins are switched dynamically, sometimes used as inputs,

sometimes as outputs.

The outputs of the 68HC16 can sink 1.6 mA to ground while

letting the pin go no higher than 0.4 Volts for a "zero" and

source about .8 mA at 4.5 Volts for a "one". In terms of

control, this is a very small signal. Most relays require over

50 times more current to operate. LED's typically take 5 mA to

be visible. HC levels are such that the output is sufficient to

drive the input on one pin of one TTL device or about a dozen

of the lower power LSTTL inputs. The output is sufficient to

drive VMOS FET's and Darlingtons with an external pull up which

can in turn con trol several amps of current. Usually, however,

a buffer will be needed to do serious non-HC in terfacing.

INPUT/OUTPUT JACKS J12

TOP VIEW

FRONT (EDGE) OF CARD v

- DS o o BERR

| GND o o BKPT

| GND o o FRZ

| RST o o IP1

| +5V o o IP0

| SIZ0 o o TSTME

| SIZ1 o o N.C.

26 pin header | DS0 o o AVC

group | DS1 o o FC2

| BR o o CS4

| RAMSEL o o CS3

| BGACK o o CLKOUT

| HALT o o MODCLK

ASYNCHRONOUS SERIAL I/O

The 68HC16 has a full duplex hardware serial channel that

operates at HC levels. To use this serial channel with most

standard communications interfaces, level converters are needed.

Drivers for RS-232C and RS-422/485 drivers are on the boards. A

zero by RS-232C specification is any voltage from +3 to +15

Volts, a one is between -3 and -15 Volts. To convert the HC

signals to the voltage ranges of that interface standard, the

NMIX- 0026 Rev. 1.1 uses a single 16 pin device, the MAX232. The

MAX232 is specifically designed for this use. It not only

provides an RS-232 receiver and transmit ter pair for the

68HC16 processor, but also a spare RS-232 receiver and

transmitter pair which can be used with port lines for

handshaking or software driven UARTS, etc.. It also generates

the higher voltages needed for full RS-232 communications

standards by way of an internal charge pump. This allows output

swings of a nominal + and - 9V, even though the chip is only

supplied +5V. J2 selects between RS232 and RS422/485 serial

interfaces. With the leftmost two pins jumpered RS232 operation

is selected.

The RS-422 standard represents a newer interface now coming into

popularity, and with good reason. Unlike the RS-232 requirements

which specify a single wire voltage transmission referenced to

ground, the RS-422 standard uses a voltage differential on a

pair of conductors. While the RS-232 at full voltage drive

levels in electrically noisy environments is barely reliable at

distances to 1000 feet, RS-422 signals are considered reliable

at distances up to 4000 feet. The RS-422 drivers operate,

requiring only a single sided 5 Volt supply, over twisted pairs

of wires. A full duplex connection for RS-422 requires two

twisted pairs, one for transmit, one for receive. The shield of

the twisted pair should act as the common return path for the

signals.

The RS-485 interface uses the same specifications for its

transmitters and receivers. It, however, allows a single twisted

pair to be used for incoming and outgoing messages. This is

accomplished by having both a transmitter (with 3 state ability)

and a receiver tied in parallel to the same twisted pair.

Multiple drop point communications are possible under this

scheme (up to 64 pairs by specification). Of course, in

application the transmitter turns on and takes control of the

lines only under software control. The actual implementation of

this control will be determined by the particular protocol being

used in the communication network. Usually one master sends an

addresses message to one of multiple slaves and then turns off

its master trans mitter. The addressed slave, recognizing its

address will turn on its transmitter and respond with the

requested data.

These two interfaces are accommodated on the NMIX-0026 by the

addition of two 8 pin 75176's, with each contain a

transmitter/receiver pair. J2 routes the RXD signal to either

one fo the 75176s (U3) or the R1O of the MAX232. RS232

operation is enabled by jumpering the leftforst two pins. J8

allows U4 to be enabled either from being tied to +5 volts or

being switched by IRQ2. The rightmost two pins are jumpered for

normal RS232 operation. J4 selects between RS422 and RS485

operation. For RS232 operation the rightmost two pins are

jumpered.

ANALOG TO DIGITAL CONVERTER

The MC68HC16 provides eight multiplexed A/D channels. The

analog inputs to these channels are accessed on pins 33 through

40 on J1. These inputs can also be used for digital information

and can be configured with software for an additional 8-bit

parallel input port. Vrhp (pin 42 of J1) and Vrlp (pin 41 of

J1) are connections for a reference supply to be used with the

A/D converter. These pins connect directly to the Vrhp and Vrlp

pins on the MC68HC16 and need to be connected to a reference

supply to make the A/D converter function. Vrhp should be

connected to Vdda and Vrlp should be connected to Vssa.

External references may also be used if they are well regulated

and free of noise.

The sample amplifier in the A/D subsection of the MC68HC16 is

powered by Vdda and Vssa. This allows the sample amplifier to

accurately transfer input signal levels up to but not exceeding

Vdda and down to but not below Vssa. Should the input signal

fall outside this range, the output from the sample amplifier

will be clipped and conversion accuracy will suffer.

Data and control words associated with the A/D are memory mapped

into 32 words of address space from $FF700 - $FF73E (only the

even addresses are used). Three sets of result registers per

channel offer converted data as Right-Justified Unsigned,

Left-Justified Signed, and Left-Justified Unsigned.

The forth program TESTADC.4TH in the programming section is an

example of implementing an endless loop of repetative

conversions using all eight channels. The conversion result is

displayed on the screen, one row of conversions per line with

two spaces between each eight-bit hex value. The data in

columns 1 and 2 are channel 7 data. Data to the right of that

comes from channel 6, and so on with channel 0 data being on the

far right of the display.

Each analog input channel (J1 pins 33, 34, 35, 36, 37, 38, 39,

and 40) should be terminated to ground through a 10k ohm or

larger resistor. Doing so will prevent them floating and ensure

a zero conversion result with no voltage applied to the analog

input. A variable voltage derive from a 50k ohm pot may be used

to drive the inputs and verify operation. The center wiper of

the pot is connected to the input to the channel to be tested.

One side of the pot goes to ground, the other can be hooked to

any conveinient +5 volt source on the board. Varying the pot

should run the readout for a particular channel from 0 to FF.

If this is what you see, the A/D subsection is working properly.

ADDRESS DECODING

The chip selects of the four JEDEC sockets are generated by a

18V8Z (U2) a Prgrammable Logic Device. Address configurations

supporting the use of 8k, 16k 32k, 64k, 128k, 256k, and 512k

static ram memories are defined by jumper settings on

configuration block J20. Configuration block J27 allows the

use of 8k, 16, 32k, 64k, 128k, 256k, 512k, and 1024k EPROMS in

U9 and U11. Memory socket U9 is the upper data byte (even), and

U11 is the lower data byte (odd). The RAM is similarly

interleaved with U8 being the upper half and U10 being the lower

half. A complete diagram of setting jumpers at J27 and J20 for

each of the devices mentioned abouve is given in the section on

SOCKET JUMPER SETTINGS.

POWER SUPPLY

The power supply circuit on the NMIX-0026 is designed to allow

the board to operate from a simple, low-voltage, AC

wall-transformer. It has three major sub circuits,

rectification, regulation and DC to DC conversion. Battery

backup capabilities are also provided to the 32 pin JEDEC

sockets and the 68HC16 internal RAM, and a power-up power-down

reset circuit.

The bridge rectifier converts the AC to DC. The 7805 regulates

this rectified incoming voltage to a constant 5 Volts. The

upper limit of unregulated DC input to the 7805 is set by the

ability of the 7805 to dissipate heat. If a heat sink is added

to the 7805, voltages in excess of 20 Volts are possible.

Driving the 7805 too hard, however, will cause it to enter

thermal overload and "shut down" its output.

The typical current required by the NMIX-0026 with 8K CMOS RAM

and the Max-FORTH ROM at 16.78 mHz from 9 VAC is 20 mA. An AC

"wallbug" style supply delivering 6 to 10 VAC RMS at more than

50 mA. is adequate to power the board. Terminal, J10, is

provided with mounting holes to solder in a standard

'barrel-style' AC power connector used with most wall bug style

supplies. With CR1 installed you can use virtually any wallbug

style supply (AC or DC and you don't need to be concerned about

polarity with the DC supply). The overriding requirement is to

have about 8 volts DC input for the 7805 while the system is

under full load..

BATTERY BACKUP

The battery backup capability allows data retention in otherwise

volatile CMOS RAMs and the processor's own internal RAM through

main-board power-downs. A third terminal on the power connector,

J7, is marked VIN. This the connection for Voltage Battery

Backup.

The VIN terminal on J7 is connected to the VBB supply rail on

the board by diode, D1. The VBB supply rail supplies the four 32

pin JEDEC sockets, the 8054HN low voltage indicator in the reset

circuit, and the MC68HC16 processor. If no power is applied to

the VIN terminal, the VBB rail is supplied through the intrinsic

diode of P channel FET, Q1, to within a diode drop of the

supplying 5 volt rail (~4.4 Volts). When the 8054HN low voltage

indicator releases the reset line, Q1 is turned on and the VBB

comes almost completely up to the 5 volt rail (~4.95 Volts).

(This may cause some problem with the Dallas Semiconductor

DS1223 bat tery sockets, as they "write protect" their RAMs at

4.75 Volts. Running an elevated 5 Volt supply may be necessary

to accommodate these parts. The purpose of this feature is,

however, to do away with the need for those devices in final

system configurations.)

When the 8054HN low voltage indicator holds the reset line low

(when VBB is below 3.8-4.2 Volts), Q1 is turned off and the

address decoder is disabled through the same input that is used

by MEMDIS. This "access" protects the memories during the power

down cycle.

To meet the full letter of the specifications of the parts

involved the correct backup voltage on the VBB pin is critical.

This supply must be low enough to ensure that after the diode

drop of D1, the VBB rail cause the 8054HN to issue a reset (~4.0

Volts), otherwise Q1 will remain on and the whole system will be

powered by VBB. It must also be high enough to ensure that after

the diode drop of D1, the VBB rail will meet the processors

required backup voltage (listed as 4.0 Volts). Therefore, the

ideal voltage for the VBB supply is 4.3-4.5 Volts. It should be

pointed out, however, the Motorola specification appears to be

overly conservative. By empirical test, VBB supplies below 3

Volts appear to be quite adequate. Most CMOS RAMs will retain

data down to 2.2 Volts. Accounting for the diode drop under such

low currents, the VBB supply may work as low as 2.5 Volts.

The processor battery backup supply enters the chip via the

Vdds pin. For backup of the processor's RAM to be successful

Vstby is connected to Vddsin on the circuit card. When the VBB

supply is used on the processor, it will retain its User Area

through power down and remember its linkages to the external

FORTH dictionary.

BOARD MOUNTING

The NMIX-0026 has six through holes intended for mounting the

card. Each hole is deilled at 0.110 inches, clearance for 4-40

hardware. Use caution when installing to prevent inadvertent

grounding of printed circuit board traces. The mounting hole

just below J13 is the only that has a trace located nearby.

Additional boards may be stacked above or below, as desired, on

the female of male side of the Vertical Stacking Connector

(VSC).

Common, 3/4 inch long, hex standoffs with a male screw on one

end and a female threaded hole on the other are ideal interboard

connection devices. The VSC connector was designed to work with

this size spacer, giving reliable board to board mounting.

The length of the standard spacer, 0.750 inches, plus the board

thickness, 0.061 inches, gives a nominal board to board spacing

of 0.811 inches. Should an exact spacing of 0.800 inches be

required, as in the case of standard mounting hardware haviong

0.800 inch PCB card guides, The standard spacer will have to mbe

milled to reduce its length by 0.011 inches.

TROUBLESHOOTING

As always the first thing to do when troubleshooting is to check

the power and ground connections. An oscilloscope should be used

to check signals. The heat sink of the 7805 is a con venient

place to hook a ground clip. If +5 Volts is present at J7 and

the board is not operational, the next item to check is the

oscillator. Putting the scope on CLKOUT (Pin 24 J12) should

show a high frequency sine wave varying from about .5 Volt lows

to 4.5 Volt peaks. If the clock signal is not present check

to see if there is +5V present at the power pin Vdd (Pins 1,

and 59 on U1). An accessible test point for this check is

either end of L2. If the clock signal is not present and Vdd

is at +5 volts, then either the MC68HC16 or the crystal are bad

and require replacement. There is one exception. If the

processor has executed a STOP instruction, the oscillator will

stop. When the oscillator is functioning correctly a clean

running square wave should be present at the CLKOUT. The CLKOUT

signal drives the timing for all external memory transfers. This

signal should transition nearly rail to rail, a 0.4V low and a

4.6V high are normal. Less amplitude can indicate a board short

or an excessive load on the line external to the MC68HC16.

The serial channel should send a sign-on message to the

terminal. If not, the reset circuit could be bad, the serial

converter (U5) could have failed, or the MC68HC16 could be

defective. With the reset button depressed the RESET line (Pin

44 J1) should be at ground. When release, the pin should rise

to 5 Volts in about a quarter second. If the reset pin is

working and still no message is seen on the terminal, check TXD,

the serial output line, at pin 11 on U5. When reset is

exercised, this line should go from normally high through a

multitude of toggles back to a high state. The periods of the

toggle transitions are multiples of approximately 100

microseconds. If this signal is not present, and there are no

user ROMs in the board, the MC68HC16 is suspect. If the signal

is present, check pin 3 of the DB25F connector. It should

normally be at -V (-9 Volts nominally) and should toggle to +V

(+9 Volts nominally) at the same rate as the serial output line.

If this is happening and no message is seen, the RS-232 wiring

or the terminal is suspect. Check to see if J6 is connected to

the DB25F RS-232 connector as follows:

J6 DB25F Signal Name

------ ----- ------ ----

n/c 1 Case ground

5 2 Serial in (to NMIX-0026)

3 3 Serial out (from NMIX-0026)

9 7 Electrical ground

Check the voltages on pins 2 and 3 of the DB25 connector. If

pin 3 is very negative and pin 2 is floating, both systems are

trying to talk on the same line. Pins 2 and 3 need to be

swapped. Usually this is done with a "null modem" inserted where

the two systems connect.

If the -V/+V signal was not found at pin 3, the RS-232 converter

is not working. Check pin 2 of the MAX232 for +V and pin 6 of

the MAX232 for -V. If these signals are not present, the charge

pump of the MAX232 has failed. Pin 14 of the MAX232, the output,

should look the same as pin 5 of J6.

Check pin 3 of J6 which is the serial into the board from the

terminal. It should normally be at a negative voltage between -3

and -15 Volts. When a key is pressed on the terminal it should

pulse to positive voltages between +3 and +15 Volts. If it

doesn't, the terminal or the RS-232 wiring are suspect. The same

signals at inverted TTL levels, should also be at RXD, which is

the serial input line of the processor.

The most common error in trying to use the NMIX-0026 is

mismatched baud rates or bit set tings. Verify that the terminal

is set for 9600 baud with one start bit, eight data bits and one

stop bits, with no parity generated. Also, make sure that the

terminal software is set up properly. For example, when using a

PC as a terminal, MAXTALK is used when connected to COM1 while

MAXTALK2 is used when connected to COM2. (Review this

discussion in the Getting Started section.)

MEMORY MAP

The MC68HC16 offers the user an contiguous address space of 1

megabyte which is split into 16-64kbyte banks. On power up, the

1k byte internal ram on the MC68HC16 maps to $00000 so that it

will be avialable to the user even if there is no additional

external ram available.

K# HEX

1024 $FFFFF +----------------------+

|Bank 15 INT REGS |

960 $F0000 |----------------------|

|Bank 14 |

896 $E0000 |----------------------|

|Bank 13 |

832 $D0000 |----------------------|

|Bank 12 |

768 $C0000 |----------------------|

|Bank 11 |

704 $B0000 |----------------------|

|Bank 10 |

640 $A0000 |----------------------|

|Bank 9 |

576 $90000 |----------------------|

|Bank 8 |

512 $80000 |----------------------|

|Bank 7 |

448 $70000 |----------------------|

|Bank 6 |

384 $60000 |----------------------|

|Bank 5 |

320 $50000 |----------------------|

|Bank 4 |

256 $40000 |----------------------|

|Bank 3 |

192 $30000 |----------------------|

|Bank 2 |

128 $20000 |----------------------|

|Bank 1 |

64 $10000 |----------------------|

|Bank 0 RESET+VECT |

+----------------------+

MISCELLANEOUS JUMPERS

# SOURCE DESTINATION NORMALLY

-------- ------------------ ------------------ --------

J2

R1O-J2,2 U5 PIN 12 U1 PIN 17 CLOSED

J2,2-RO U1 PIN 17 U3 PIN 1 OPEN

J4

IRQ2-J4,2 U1 PIN 77 U3 PIN 2&3 OPEN (485)

J4,2-GND U3 PIN 2&3 GROUND

CLOSED(422)

J8

IRQ2-J8,2 U1 PIN 77 U4 PIN 2&3 OPEN

J8,2-+5V U4 PIN 2&3 +5 VOLR RAIL CLOSED

GENERAL PURPOSE SOCKETS

JUMPER 1 o o 32 +5

A16 2 o o 31 JUMPER

JUMPER 3 o o 30 JUMPER

A12 4 o o 29 JUMPER

A7 5 o o 28 JUMPER

A6 6 o o 27 A27

A5 7 o o 26 A9

A4 8 o o 25 A11

A3 9 o o 24 OE

A2 10 o o 23 A10

A1 11 o o 22 CHIP SELRCT

A0 12 o o 21 IO/7

IO/0 13 o o 20 IO/6

IO/1 14 o o 19 IO/5

IO/2 15 o o 18 IO/4

GND 16 o o 17 IO/3

A15 A16 A19 VBB VBB R/W

O O O O O O

VBB O O O O O O O O

O O O O O O O

A16 A19 +5 A18 A14 A15 VBB

GENERAL PURPOSE SOCKET - U8, U9, U10, U11

MEMORY JUMPER SETTINGS

Jumper Settings for Standard JEDEC 28/32/36 Pin Devices

8K X 8 DEVICES

2764, 2864, 6264

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| | | | X | X | X |-----+

| XXXXXXX | | | X | X | X | |

+-----| | | | | | | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

16K X 8 EPROM

27128

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| | | | X | | X |-----+

| XXXXXXX | | | X | X | X | |

+-----| | | | | X | | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

32K X 8 EPROM

27256

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| | | | X | | |-----+

| XXXXXXX | | | X | X | X | |

+-----| | | | | X | X | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

32K X 8 RAM

62256

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| X | | | X | | X |-----+

| | X | | | X | X | X | |

+-----| | | | | X | | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

64K X8 EPROM

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| | | | X | | |-----+

| | X | | | X | X | X | |

+-----| X | | | | X | X | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

128K X 8 RAM

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| X | X | X | X | | X |-----+

| | X | X | X | X | X | X | |

+-----| | | | | X | | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

256K X 8 RAM/512K X 8 RAM

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| X | X | X | | | X |-----+

| | X | X | X | X | X | X | |

+-----| | | | X | X | | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

128K X 8, 256K X 8, 512K X 8, 1024K X 8 EPROM

A15 A16 A19 VBB VBB R/W

+-----+-----+-----+-----+-----+-----+

+-----| | | | | | |-----+

| | X | X | X | X | X | X | |

+-----| X | X | X | X | X | X | |

+-----+-----+-----+-----+-----+-----+-----+

VBB A16 A19 VBB A18 A14 A15 VBB

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

To write protect the ram use the same addressing scheme jumpers

given in the previous examples but add the following pull up

resistor.

REMOVE THIS JUMPER ----+

|

|

|

A15 A16 A19 VBB VBB R/W |

+-----+-----+-----+-----+-----+--|--+ VBB

+-----| | | | | | | |-----+

| | X | X | X | X | X | X | |

+-----| X | X | X | X | X | X | |

+-----+-----+-----+-----+-----+-----+--|--+

VBB A16 A19 VBB A18 A14 A15 |

|

|

|

ADD A 100K 1/4 4 5% RESISTOR ACROSS THESE PINS---+

(+5 PIN3 PIN1 PIN28 PIN29 PIN30 PIN31)

(CENTER PIN DESIGNATION)

INPUT/OUTPUT JACKS

EXPANSION JACK J13

D14 o o D15

D12 o o D13

D10 o o D11

D8 o o D9

GND o o GND

GND o o GND

GND o o GND

GND o o GND

GND o o GND

GND o o GND

NC o o A19

A17 o o A18

AS o o BHE

MEMDIS o o BLE

E o o RST

A16 o o IRQ1

A15 o o +5

A13 o o R/W

A8 o o A14

A7 o o A9

A6 o o A10

A5 o o A12

A4 o o OE

A3 o o A11

A2 o o AS64

A1 o o D7

D0 o o D6

D1 o o D5

D2 o o D4

GND o o D3

The J13 expansion connector was designed to follow the JEDEC

stan dard for byte sized memory parts in the 8, 16 and 32K Byte

varieties. The J4 connector on these boards are made to most

closely match the more recently available 32K JEDEC parts.

SERIAL INPUT/OUTPUT JACK J11 (RS442/485)

TOP VIEW

(PIN 1) N.C. o o NC

+422XMT o o -422XMT

GND o o GND

-422RCV o o +422RCV

N.C. o o N.C.

SERIAL INPUT/OUTPUT JACK J6 (RS232)

TOP VIEW

(PIN 1) N.C. o o TO J6-5

SI o o TO J6-6

SO o o TO J6-4

TO J6-2 o o N.C.

GND o o N.C.

FACTORY DEFAULT SETTING FOR RS232

+---+---+---+

| XXXXX | o | J2

+---+---+---+

+---+---+---+

| o | XXXXX | J8

+---+---+---+

+---+---+---+

| o | XXXXX | J4

+---+---+---+

PROGRAMMING EXAMPLES

The following programming example deals with the Analog to

Digital Converter subsection. The program excercises all eight

channels of the A to D. Conversion results are displayed on the

terminal screen as rows of data scrolling in columnar form. The

far left two columns contain conversion data from channel 7.

Data from channel 6 is the the right of that, and so on with

channel 0 at the far right of the display.

The data inputs are connected to pins 33 through 40 on J1. Each

channel is connected between one of these pins and ground. Each

input is also terminated to ground through a 1k ohm 1/4 watt

resistor. Termination to ground ensures each channel will be at

a conversion value of zero when no analog signal is applied.

Vrlp, (pin 41) of connector J1, must be connected to Vssa.

Vrhp, (pin 42) of connector J1, must be connected to Vdda.

These connections set the reference voltage for the A/D. The

example sets up an 8-bit conversion giving a range of 00 to FF

for voltages ranging from 0 VDC to 5 VDC. The converter is also

capable of doing 10 bit conversions. The input channels of the

A/D can also be used as digital inputs for standard TTL and CMOS

digital levels. Concurrent use as analog or digital use is

possible as long as the channels are not required to do A/D

conversion and digital input at the same time. For instance,

since each channel has a conversion complete flag in the status

byte, this flag could be used to indicate availablitlity for

digital use after an analog conversion has been completed and

before the next one is allowd to begin.

Shown below is a summary of the determination of the various

data used to initialize the registers in the programming

example. More detailed information is avialable in the Motorola

Refernce Manual for the MC68HC16.

ADCMCR FF700

|0|0|0|X|X|X|X|X|X|0|X|X|X|X|X|X| = 0000

| | | |

| | | +--SUPV BIT, NO EFFECT ON HC16Z1

| +-+-FREEZ RESPONSE-SET TO IGNORE

+--BECOMES '1' AFTER RESET. SETTING '0' TURNS ON

PORTADA FF706

|0|X|X|X|X|X|X|X|7|6|5|4|3|2|1|0| = WRITE ONLY

| | | | | | | | |

| +-+-+-+-+-+-+-+--- PADA(0-7)

|

+---- SHOWS 0 AFTER RESET

Channels may be used for input or digital input. They

MUST be used for analog input, but can be used for

digital input after an A/D cnversion is complete and

before another begins.

ADCTL0 FF70A

|1|X|X|X|X|X|X|X|1|1|1|1|1|1|1|1| = FFFF

| | | | | | | | |

| | | | +-+-+-+-+-PRESCALE RATE SCLK/64

| | +-+-SAMPLE TIME 32 A/D CLK PERIODS

| +--10 BIT MODE SET (0 FOR 8-BIT MODE)

+--BECOMES '0' AFTER RESET. SETTING '1' TURNS ON

ADCTL1 FF70C

|1|X|X|X|X|X|X|X|X|1|1|1|0|1|1|1| = FFF7

| | | | | | | |

| | | +-+-+-+-+-+-AN[0:7] RSLT[0:7]

| | | |MULTIPLE 8 CHANNEL CONVERSION

| +-+-+SEQUENCES

+- SHOWS '0' AFTER RESET, '1' TURNS ON

ADSTAT FF70E

|d|X|X|X|X|d|d|d|7|6|5|4|3|2|1|0| = READ ONLY

| | | | | | | | | | | |

+-SEQ | | | +-+-+-+-+-+-+-+

COMPLETE | | | +CHANNEL STATUS BITS

WHEN '1' | | | '1'= CONVERSION COMPLETE

| | | REVERTS TO '0' ON READING RESULT

| | |

+-+-+--VALUE IS # OF NEXT RESULT REGISTER

TO BE WRITTEN

A/D RESULT REGISTER CHANNELS:

0 1 2 3 4 5 6 7

FF710 FF712 FF714 FF716 FF718 FF71A FF71C FF71E

right justified unsigned

FF720 FF722 FF724 FF726 FF728 FF72A FF72C FF72E

left justified signed

FF730 FF732 FF734 FF736 FF738 FF73A FF73C FF7E3

left justified unsigned

( TESTADC1.4TH )

( FEB 2, 1995 )

( BY FRANK KAMP )

COLD

HEX

FF700. 2CONSTANT ADCMCR ( module configuration reg addr

FF70A. 2CONSTANT ADCTL0 ( ADC control reg 0

FF70C. 2CONSTANT ADCTL1 ( ADC control reg 1

FF70E. 2CONSTANT ADSTAT ( ADC status reg

FF710. 2CONSTANT CH-0 ( channel 0 digital output

FF712. 2CONSTANT CH-1 ( channel 1 digital output

FF714. 2CONSTANT CH-2 ( channel 2 digital output

FF716. 2CONSTANT CH-3 ( channel 3 digital output

FF718. 2CONSTANT CH-4 ( channel 4 digital output

FF71A. 2CONSTANT CH-5 ( channel 5 digital output

FF71C. 2CONSTANT CH-6 ( channel 6 digital output

FF71E. 2CONSTANT CH-7 ( channel 7 digital output

: INIT0 0000 ADCMCR L! ; ( turns on A/D subsection

: INIT1 FF7F ADCTL0 L! ; ( 8-bit,16clkp,clk/64

: CONVERT FFF7 ADCTL1 L! ; ( cont conv,8ch,AN[0:7]

: DELAY 1000 0 DO LOOP ; ( simple delay loop

: READ-STATUS ADSTAT L@ ; ( reads status register

: TEST-CH-5 20 AND 0= ; ( tests ch5 for a '1'

: TEST-FOR-FIVE ( loops until ch5 conversion complete

BEGIN

READ-STATUS

TEST-CH-5

UNTIL ;

: DISPLAY

CH-7 L@ 4 U.R ( The display routine outputs digital

CH-6 L@ 4 U.R ( data in columnar format across scren

CH-5 L@ 4 U.R ( starting with ch7 at the far left.

CH-4 L@ 4 U.R ( Display scrolls down screen as conversions

CH-3 L@ 4 U.R ( progress.

CH-2 L@ 4 U.R

CH-1 L@ 4 U.R

CH-0 L@ 4 U.R ;

: TESTADC ( Main routine

INIT0 ( A/D on

INIT1 ( initialization

BEGIN

CONVERT ( initialization and start conversion

TEST-FOR-FIVE ( checks for conversion complete

DISPLAY ( outputs result to screen

DELAY ( fixed wait to slow display

CR ( goes to next display line

?TERMINAL ( loop ends on any key depress

UNTIL ; ( loops to BEGIN

REGISTERS

K# HEX

1024 $FFFFF +----------------------+

|----------------------|

$FFDFF |----------------------|

|QSM 512 BYTES |

$FFC00 |----------------------|

$FFB07 |----------------------|

|SRAM CTRL 8 BYTES |

$FFB00 |----------------------|

$FFA7F |----------------------|

|SIM 128 BYTES |

$FFA00 |----------------------|

$FF93F |----------------------|

| GPT 64 BYTES |

$FF900 |----------------------|

$FF73F |----------------------|

| ADC 64 BYTES |

$FF700 |----------------------|

|----------------------|

+----------------------+

ADC SUBSECTION

FF700 (ADCMCR) Module Configuration

FF702 (ADTEST) Factory Test

FF704 RESERVED

FF706 (PORTADA) Port ADA data

FF708 RESERVED

FF70A (ADCTL0) ADC control 0

FF70C (ADCTL1) ADC control 1

FF70E (ADSTAT) ACD status

FF710-FF71E (RJURR0-RJURR7) Right-Justified unsigned results

FF720-FF72E (LJSRR0-LJSRR7) Left-Justified signed results

FF730-FF73E (LJURR0-LJURR7) Left-justified unsigned results

GPT SUBSECTION

FF900 (GPTMCR) Module configuration

FF902 RESERVED

FF904 (ICR) Interupt configuration

FF906 (DDRGP) PGP data direction (PORTGP) PGP data

FF908 (OC1M) OC1 action mask (OC1D) OC1 Action data

FF90A (TCNT) TIMER COUNTER

FF90C (PACTL) PA Control (PACNT) PA Counter

FF90E (TIC1) Input capture 1

FF910 (TIC2) Input capture 2

FF912 (TIC3) Input capture 3

FF914 (TOC1) Output compare 1

FF916 (TOC2) Output compare 2

FF918 (TOC3) Output compare 3

FF91A (TOC4) Output compare 4

FF91C (TI4/05) Input capture 4 / Output compare 5

FF91E (TCTL1) Timer ctrl 1 (TCTL2) Timer ctrl 2

FF920 (TMSK1) Timer mask 1 (TMSK2) Timer mask 2

FF922 (TFLG1) Timer flag 1 (TFLG2) Timer flag 2

FF924 (CFORC) Force compare (PWMC) PWM control C

FF926 (PWMA) PWM control A (PWMB) PWM control B

FF928 (PMCNT) PWM Count

FF92A (PWMBUFA) PWMA Buffer (PWMBUFB) PWMB Buffer

FF92C (PRECSL) PRESCALER(lower 9 bits)

FF92E-FF93F RESERVED

SIM SUBSECTION

FFA00 (SCIMCR) SCIM Configuration Register

FFA02 (SCIMTR) Module Test

FFA04 (SYNCR) Clock Synthesizer Control

FFA06 UNUSED (RSR) Reset status register

FFA08 (SCIMTRE) Module Test E

FFA0A (PORTA) Port A Data (PORTB) Port B Data

FFA0C (PORTG) Port G Data (PORTH) Port H Data

FFA0E (DDRG) Port G Data Dir (DDRH) Port H Data Dir

FFA10 UNUSED (PORTE0) Port E Data

FFA12 UNUSED (PORTE1) Port E Data

FFA14 (DDRAB) Port A/B Data Dir (DDRE) Port E Data Dir

FFA16 UNUSED (PEPAR) Port E pin assig

FFA18 UNUSED (PROTF0) Port F Data

FFA1A UNUSED

FFA1C UNUSED (DDRF) Port F Data Dir

FFA1E UNUSED (PFPAR) Port F pin assign

FFA20 UNUSED

FFA22 (PICR) Periodic Interupt Control

FFA24 (PITR) Periodic Interupt Timing

FFA26 UNUSED (SWSR) Software Service

FFA28 UNUSED (PROTFE) Port F edge det flags

FFA2A UNUSED (PFLVR) Port F edge det int vector

FFA2C UNUSED (PFLVR) Port F edge det int level

FFA2E UNUSED

FFA30 (TSTMSRA) Test Module Master Shift A

FFA32 (TSTMSRB) Test Module Master Shift B

FFA34 (TSTSCA) Tst Mod Cnt A (TSTSCB) Tst Mod Cnt B

FFA36 (TSTRC) Test Module Repetition Counter

FFA38 (CREG) Test Module Control

FFA3A (DREG) Test Module Distributed Register

FFA3C UNUSED UNUSED

FFA3E UNUSED UNUSED

FFA40 UNUSED (PORTC) Port C Data

FFA42 UNUSED UNUSED

FFA44 (CSPAR0) Chip-Select pin assignment 0

FFA46 (CSPAR1) Chip-Select pin assignment 1

FFA48 (CSBARBT) Chip-Select base address boot

FFA4A (CSORBT) Chip-Select option boot

FFA4C (CSBAR0) Chip-Select base 0

FFA4E (CSOR0) Chip-Select option 0

FFA50 UNUSED

FFA52 UNUSED

FFA54 UNUSED

FFA56 UNUSED

FFA58 (CSBAR3) Chip-Select base 3

FFA5A (CSOR3) Chip-Select option 3

FFA5C UNUSED

FFA5E UNUSED

FFA60 (CSBAR5) Chip-Select base 5

FFA62 (CSOR5) Chip-Select option 5

FFA64 (CSBAR6) Chip-select base 6

FFA66 (CSOR6) Chip-Select option 6

FFA68 (CSBAR7) Chip-Select base 7

FFA6A (CSOR7) Chip-Select option 7

FFA6C (CSBAR8) Chip-Select base 8

FFA6E (CSOR8) Chip-Select option 8

FFA70 (CSBAR9) Chip-Select base 9

FFA72 (CSOR9) Chip-Select option 9

FFA74 (CSBAR10) Chip-Select base 10

FFA76 (CSOR10) Chip-Select option 10

FFA78 UNUSED

FFA7A UNUSED

FFA7C UNUSED

FFA7E UNUSED

SRAM CTRL SUBSECTION

FFB00 (RAMMCR) RAM Module Configuration Register

FFB02 (RAMTST) RAM Test Register

FFB04 (RAMBAH) RAM Array base address register high

FFB06 (RAMBAL) RAM Array base address register low

QSM SUBSECTION

FFC00 (QSMCR) QSM Module Configuration

FFC02 (QTEST) QSM Test

FFC04 (QUILR) QSM Interupt Level (QIVR) QSM interrupt vector

FFC06 RESERVED

FFC08 (SCCR0) SCI Control 0

FFC0A (SCCR1) SCI Control 1

FFC0C (SCSR) SCI Status

FFC0E (SCDR) SCI Data

FFC10 RESERVED

FFC12 RESERVED

FFC14 RESERVED (PORTQS) PQS Data

FFC16 (QSPAR) PQS pin assign (DDRQS) PQS Data direction

FFC18 (SPCR0) SPI Control 0

FFC1A (SPCR1) SPI Control 1

FFC1C (SPCR2) SPI Control 2

FFC1E (SPCR3) SPI Control 3 (SPSR) SPI Status

FFC20-FFCFF RESERVED

FFD00-FFD1F REC.RAM

FFD20-FFD3F TRAN.RAM

FFD40-FFD4F COMD.RAM

.

NMIX-0026 PARTS LIST

REF.DES. VALUE COMPONENT

--------------------- ---------- -------------------------

C1,2 100uF 25V Electrolytic

C4-7 10uF 16v Electrolytic

C8 (not used)

C3,9-11, C17-20 0.1uF 10v Disk Ceramic

C22-25,28,30,32

C12,13 (not used)

C14,16 22pF 10v Disk ceramic

C15 0.1mF 50v Polyester/Mylar

C16 (not used)

C21 (not used)

C26,27 1.0mF 25v Tantalum

C29 100uF 16v Electrolytic

C31 0.01uF 10V Disk ceramic

R1 330k,1/4w,5% Resistor

R2 10meg,1/4w,5% Resistor

R3,4 (not used)

R5,6,8,9,11,12 10k,1/4w,5% Resistor

R7 (not used)

R10 1.0k,1/4w,5% Resistor

U1 MC68HC16Z1 Microprocessor

U2 18V8Z PAL

U3,4 75176 IC

U5 MAX232 IC

U6-7 (NOT USED)

U8,10 681000 128K X 8 SRAM

U9 27C256 HI BYTE ROM

U11 27C256 LO BYTE ROM

LVI1 8054 IC

VR1 LM7805 REGULATOR

CR1 VM08 BRIDGE RECTIFIER

D1 1N4148 SILICON DIODE

Q1 VP0300M FET

L1,2,3 10uH INDUCTOR

SW1 RESET SWITCH

132 PIN PLCC SOCKET U1

20 PIN DIP SOCKET U2

8 PIN DIP SOCKET U3, U4

16 PIN DIP SOCKET U5

32 PIN DIP SOCKET U8,9,10,11

J20,27 2 PIN SOCKET

1X6 2EA HEADER

1X7 1EA HEADER

J10 POWER JACK CONNECTOR

Y1 32.768kHz XTAL

J13 VS 60 PIN CONNECTOR

VS 34 PIN SPACER

J1 3 PIN TERMINAL BLOCK

RS1,2 10K 9E10L RESISTOR SIPP

J6,11 2X5 DBL PIN HEADER

J2,4,8 1X3 PIN HEADER

NMIX-0026 PCB

SHUNTS

NMIX-0026 V2.0 SILKSCREEN

SCHEMATIC V2.0

INTEL FORMAT DUMP COMMAND

The following Forth program allows a section of memory to be

dumped out the serial channel in the Intel hex format which is a

standard used by many of the commercially available PROM

programmers. This program should allow the use of such

programmers to capture programs and data in EPROMs, which are

not supported for programming by the NMIX-0026 directly.

HEX

VARIABLE CHKSUM

: CE DUP A < IF 30 ELSE 37 THEN + EMIT ; ( CONVERT AND EMIT )

: 2.R FF AND 10 /MOD CE CE ;

: 4.R 0 100 UM/MOD 2.R 2.R ;

: INTEL-DUMP ( addr count --- )

OVER + SWAP ( CONVERTS ADDR & COUNT TO UPPER, LOWER ADDR )

BEGIN

CR

2DUP 20 + MIN ( MAKE NEXT LINE OF OUTPUT UP TO 32 BYTES LONG)

SWAP ( BRING UP START ADDRESS, MOVE DOWN END ADDRESS )

." :" ( BEGIN THE RECORD )

2DUP - ( FIND OUT # OF BYTES IN THIS RECORD )

DUP CHKSUM ! ( BEGIN CHKSUM COMPUTATION )

2.R ( PRINT # OF BYTES IN RECORD IN TWO DIGIT FIELD )

DUP 100 /MOD + CHKSUM +! ( ADD START ADDRESS TO CHKSUM )

DUP 4.R ( PRINT START ADDRESS IN FOUR DIGIT FIELD )

." 00" ( PRINT RECORD TYPE, NO NEED TO ADD TO CHKSUM )

>R DUP R> ( MAKE START STOP #S FOR DO LOOP )

DO

I C@ 2.R ( PRINT HEX BYTE IN TWO DIGIT FIELD )

I C@ CHKSUM +! ( UPDATE CHKSUM )

LOOP

CHKSUM @ FF AND NEGATE 2.R ( PRINT CHKSUM NEG 2 DIGIT FIELD )

2DUP =

UNTIL ( KEEP GOING TILL LINE END IS = TO BLOCK END )

CR ." :00000001FF" CR ( TACK ON END RECORD )

2DROP

;

Program and application courtesy of Danny Barger, International

Computing Scale.