New
Micros, Inc
1601
Chalk Hill Road
Dallas,
TEXAS 75212
Phone:
(214) 339-2204
Fax:
(214) 339-1585
Email:
nmitech@newmicros.com
GETTING
STARTED
The
NMIX-0020-S1, is an F68HC11 based
single board computer
with
built-in LCD display interface and a 4x5 matrix keypad
interface. When
purchased in development configuration,
it is
complete
and ready to run. The NMIT-0020-S1 is
a target
version of
the NMIX-0020-S1. It
is made from the same
printed
circuit board as the NMIX-0020-S1, but has fewer parts
installed. Normally,
a developer will use the NMIX-0020-S1
for
development, and high end projects,
then switch to the
lower
cost NMIT-0020 when volume buying begins.
To
operate the NMIX-0020-S1 system, apply
+5 volts at J3 and
connect
a terminal to the serial RS-232 DB25F
connector.
Most
terminals should plug in directly, with
a straight through
cable (i.e.: pin 1 to pin 1, 2 to 2, 3 to 3,
etc.). The
NMIX-0020-S1
uses only lines 2 and 3 for serial in and serial
out
respectively, and pins 1 and 7 for ground.
Many terminals
require
additional handshaking signals to
work, so pins 4 and
5 are
hooked together on the DB25F connector, as are pins 6 and
20. In this way the terminals that
require the additional
handshake
signal have their own " clear to send" / "ready to
send"
and "data terminal
ready" / "data
set ready" signals
wrapped
back around, indicating
"always ready".
RS-232 connections:
J6 DB9F DB25F
Signal Name
--- ---- -----
------ ----
5 1 Case ground
6 3 2 Serial in to SBC
7 2 3 Serial out from SBC
8 5 7 Electrical ground
7 to 8 4 to 5 CTS to RTS
4 to 6 6 to 20 DSR to DTR
In
order to talk to the NMIX-0020-S1 the terminal must have the
correct
bit settings. The baud rate should be
set at 9600 baud
for
the standard 2 Mhz system (8 Mhz
crystal). The
NMIX-0020-S1
sends and receives a bit protocol of one start bit,
eight
data bits and one stop bit.
+---+---+---+---+---+---+---+---+---+---+
| S | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | S |
+---+---+---+---+---+---+---+---+---+---+
When
the terminal is set correctly, every
time you depress
and
release the reset button the NMIX-0020-S1 should respond
with:
Max-FORTH V3.x (Assuming you
are using the Forth)
Seeing that
message means the terminal can see the
NMIX-0020-S1. Press "return" on your terminal
several times.
If the
NMIX-0020-S1 responds with "OK" each time, communications
are
established.
NMIX
AND NMIT DIFFERENCES:
The NMIT-0020-S1, when purchased in the
generic target
configuration, is a minimum, 5 Volt only,
configuration.
The
F68HC11, Xtal, reset circuit,
various HC "glue"
components
and three 28 pin JEDEC sockets. Typically, a
program developed
in the "development configured" board will
be
installed in the "generic target configured" board for
production
of a dedicated application. The user must install
the
appropriate jumpers, which are not
provided in the target
configuration.
All
configurations of the F68HC11 based NMIX-0020-S1 boards use
the same
base PC board. Configuration
differences refer to
the
extent to which the board is filled with components.
PARALLEL
PORTS
The
F68HC11 has five parallel ports, Port A, B, C, D and E.
Two
ports of the F68HC11 are sacrificed to create a 64K
address
and data bus. Although some of the
remaining port lines
have
special multiplexed functions, they can
all be used as
inputs
or as outputs according to
their individual designs.
Some of
the port lines have direction registers allowing them to
be used
as either inputs or outputs. The three
remaining ports
of the
F68HC11 are brought out to connector J5.
Power and
ground
are also available on J5.
INPUT/OUTPUT JACK J5
TOP VIEW
FRONT (EDGE) OF CARD v
- X PD5 o o PD4 X
| X PD3 o o PD2 X
| X PD1 o o PD0 X
|
+5 o o +5
|
GND o o GND
| X PA7 o o PA6 O
| O PA5 o o PA4 O
34 pin header | X PA3 o o PA2 I
group | I PA1 o o PA0 I
|
+5 o o +5
|
GND o o GND
| I PE7 o o PE6 I
| I PE5 o o PE4 I
| I PE3 o o PE2 I
| I PE1 o o PE0 I
|
+5 o o +5
-
GND o o GND
I=INPUT O=OUTPUT X=EITHER
These
lines can be used as individual inputs, outputs or in
combination. There are very few applications, however, where
pins
are switched dynamically, sometimes used as inputs,
sometimes
as outputs.
A voltage
of 7/10 Vcc or greater will always be recognized as
a
logical one. Voltages 2/10 Vcc or lower
will always be
recognized
as logic 0. Voltages applied above Vcc
or below 0
Volts
can damage the computer.
The outputs
of the F68HC11 can sink 1.6 mA to ground while
letting
the pin go no higher than 0.4 Volts for a "zero" and
source
about .8 mA at 4.5 Volts for a "one". In terms of
control,
this
is a
very small signal. Most relays require
over 50 times
more
current to operate. LED's typically
take 5 mA to be
visible. HC
levels are such that the output
is sufficient to
drive
the input on one pin of one TTL device or about a dozen of
the
lower power LSTTL inputs. The output is sufficient to
drive
VMOS FET's and Darlingtons with an external pull up which
can in
turn control several
amps of current. Usually,
however, a buffer will be needed to do serious non-HC
interfacing.
KEYPAD
INTERFACE
The
NMIX-0020-S1 has a built-in Keypad Controller, the 74C923.
This
device scans matrixes of keys up to 4x5 without processor
intervention. Connection of the 74C923 Keypad Controller
to
the
cpu is via 68HC11 Port E pins PE3 thru
PE7 for key data
and Port
A pin PA0 for the key valid
strobe.
The operation
of the 74C923 Keypad Controller provides a
high
level Data Available Strobe to Port
PA0 when a
valid
key is detected
in the keyboard matrix. This
can be
detected
by the 68HC11 under software control
and the key data
can
then be read from Port E as a binary number that
represents
the valid key on the keyboard.
Connector J7
provides the keyboard
connection.
Compatible keyboards
are common and should be a
similar to
Grayhill
Series 86 or 88 keyboards. Following is
the pinout of
J7:
KEYBOARD INPUT/OUTPUT JACK J7
TOP VIEW
NUMBERED LEFT TO RIGHT
1 2 3
4 5 6 7 8 9
--------------------------
o o o
o o o o o o
C C R
R C R R C C
O O O
O O O O O O
L L W
W L W W L L
1 2 3
2 3 1 4 4 5
MULTIPLEXING
KEYBOARD AND A/D CHANNELS
It is
important to note that 5 of the 8 68HC11 Port E A/D
input
channels can not be used while the
Keyboard Controller
is
installed. If more than three A/D
channels are required the
user
may perform a simple modification to multiplex Port
E
with
the 74C923 Keyboard Controller and the A/D input
channels. Following is a brief explanation:
1.
Enable the 74C923 output enable function so that the outputs
of the
74C923 can be disabled to a high impedance condition. To
do this
you need to remove the 74C923 IC from its socket and
bend pin 14 out so that it will not plug back
into the IC
socket. Reinstall the 74C923 into its socket.
2.
Solder a wire to pin 14 on the 74C923.
Connect the other end
of this
wire to an uncommitted output pin
on the 68HC11 cpu.
For example Port A line PA4 is available at pin 14 of J5.
3. Add a software control sequence that will
cause Port A pin
PA4 to idle in the high level output
condition ( 74C923 outputs
off), output a low on PA4 (enable 74C923 outputs)
prior to
the
read of the Port E key data, and return
PA4 to the idle
high
condition after the read.
4. The A/D channels can now be used by placing
a 4.7K
ohm
resistor
or higher in series with the J5 port E inputs.
LCD
INTERFACE
The NMIX-0020-S1 has a built-in connector (J1)
and decode
circuitry
to allow direct interfacing to many of the
popularly
available, intelligent
LCD displays. A wide number of LCD
modules
can be accommodated, since many
manufacturers make the
modules
with the same controller chips or control functions.
Some of
these manufacturers are AMD, Densitron, Epson, Optrex,
Sharp,
and Sieko. They come in configurations
such as 1x8,
1x16,
2x16, 1x20, 2x20, etc., up to 4x40 or 2x80.
Connector J1
contains 16 pins but will accept
the 14 pin or
16 pin
ribbon connectors from the standard LCD modules as the
pinout is
common except for
an additional enable signal
for the
larger displays. J1 is configured to
accept ribbon
connectors
that are taken off the back side of the LCD to allow
flush
mounting of the module's display face to a front panel.
Ribbon
cables attached this way have their signals mirrored.
The LCD
interface is hard addressed at four consecutive
locations, $B5FC hex thru $B5FF hex. On board logic provides
the necessary chip select and timing information to operate
the
displays. Address line A0 goes
directly to the displays,
so each
chip select represents two memory locations. The
smaller
displays, with up to 80 characters, use
only one
display
controller chip. Those with a larger
number of
characters
use additional display controller chips.
Those with
16 pin
connectors have up to two controllers
built-in.
The type
display attached will determine
its own access
speed. Generally they are listed at 450ns. This is fast
enough for
1Mhz bus timing
(6800 and 6500 type
processors), but not fast enough for 2 Mhz. Almost all of the
displays
will work, however, at this higher
speed, although
using
them this way means they are outside the manufacturer's
listed
specification.
The
board provides little support to the display processor,
other
than providing the necessary signals,
voltages, and
gated chip selects. The handling of the displays follows the
manufacturer's specifications for the particular display.
Extensive
example program segments are shown in Appendix B for
single
controller, 2 line displays. For other
configurations
and
types refer to the manufacturer's
literature.
SERIAL
I/O
The F68HC11
has a full duplex hardware
serial channel
that
operates at CMOS levels. To use this
serial channel with
most
standard communications interfaces,
level converters are
needed. Drivers for RS-232C and RS-422/485 drivers
are on the
boards.
(It should be noted that only one combination of RS-232
driver, RS- 422
drivers or RS-485 driver should be used at one
time to
avoid contention of their receiver outputs.)
A zero by RS-232C specification is any
voltage from +3 to
+15 Volts, a one is between -3 and -15
Volts. To convert the
HC
signals to the voltage ranges of that interface standard,
the
NMIX- 0020 Rev. 1.0 uses a single 16 pin device, the ICL232.
The
ICL232 is ideally suited for this use.
It not only
provides
an RS-232 receiver and transmitter pair for the
F68HC11
processor, but also a spare RS-232
receiver and
transmitter
pair which can be used
with port lines for
handshaking
or software driven UARTS, etc..
It also
generates
the higher voltages needed for full
RS-232
communications
standards by way of an internal charge pump.
This
allows output swings of a nominal + and - 9V,
even though
the
chip is only supplied +5V. (The
negative output is also
used to
get the negative voltage bias for the display to
increase
contrast.)
The RS-422 standard represents a newer interface
now coming
into
popularity, and with good reason.
Unlike the RS-232
requirements
which specify a single wire voltage
transmission
referenced to ground, the RS-422 standard uses a
voltage
differential
on a pair of conductors. While the
RS-232 at full
voltage
drive levels in electrically noisy environments is
barely
reliable at distances to 1000 feet,
RS-422 signals are
considered
reliable at distances up to 4000
feet. The RS-422
drivers
operate, requiring only a single sided
5 Volt supply,
over
twisted pairs of wires. A full duplex
connection for
RS-422
requires two twisted pairs, one for
transmit, one for
receive. The shield of the twisted pair should act as
the
common
return path for the signals.
The
RS-485 interface uses the same specifications for its
transmitters
and receivers. It, however, allows a
single
twisted
pair to be used for incoming
and outgoing messages.
This is accomplished by having both a
transmitter (with 3
state ability) and a receiver tied in parallel to the same
twisted
pair. Multiple drop point
communications are possible
under this
scheme (up to 64 pairs by specification). Of
course,
in application the transmitter
turns on and takes
control
of the lines only under software control.
The actual
implementation of
this control will be
determined by the
particular
protocol being used in the communication network.
Usually
one master sends an addresses message to one of multiple
slaves
and then turns off its master transmitter. The
addressed
slave, recognizing its address will
turn on its
transmitter
and respond with the requested data.
These
two interfaces are accommodated on the NMIX-0020-S1 by the
addition of
two 8 pin 75176's, which
each
contain a transmitter/receiver pair.
Whether the
transmitter
of the pair is active, or not, is controlled by a
signal
on one of its pins.
One of the 75176's (U11) has its receiver
always enabled. It
is
used exclusively as the RS-422
receiver. The other 75176
(U10)
can be used as the RS-422 transmitter if jumper G on the
NMIX-0020-S1 is grounded (i.e.: in 422
position), or it can be
used as
the receiver and transmitter for the RS-485 interface
as controlled by Port A pin PA3 (i.e.: in 485
position). In
this
case if PA3 is low, the 75176's
transmitter is not active.
If PA3 is high its transmitter is active.
RS-422/485
operation requires the use of two jumper blocks
inserted
in place of U17 and U16.
The
Jumper block needed for U17 connects pin 9 to pin 13, and
pin 14
to pin 15. The jumper block needed for
U16 connects pin
9 to
pin 10.
ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
(ACIA)
The 65C51
ACIA provides the following features:
Full duplex operation with buffered
receiver and transmitter
Data set/modem control functions (DTR,
DSR, RTS, CTS, DCD)
Internal baud rate generator with 15
programmable baud rates
(50 to
19,200)
Program-selectable internally or
externally controlled receiver
rate
Programmable word lengths (5, 6, 7, 8)
Number of stop bits (1, 1.5, 2)
Parity bit generation and detection (Odd,
Even, Mark, Space)
Programmable interrupt control
Program reset
Program-selectable serial echo mode
Communications crystal for baud rate
generation
Charge pump for +9V/-9V supplies
Transceivers to allow RS-232 level
interfacing
Transceivers to allow RS-422 level
interfacing
Transceivers to allow RS-485 level
interfacing
Jumper selectable RS-422, modified RS-422,
or RS-485 operation
Setup
for RS-232 mode:
1. Remove U19 and U18 if they are present..
Install the ICL232
at U16
and the 145406 at U17.
2. Remove jumpers AA and BB. Install a shunt on jumper
location
CC so that the two right most pins are connected.
Setup
for RS-422 and RS-485 mode:
1. Install U19 and U18 if they are not present.
2. Move the shunt on jumper CC so that the left
two jumper pins
are
connected together. This will disable
RS-232 mode and
enable
RS-422/485 mode.
3. Install shunts on jumper blocks AA and
BB. For RS-422
connect
the left two pins of blocks AA and BB
together. For
RS-485
connect the right two pins of blocks AA and BB together.
RS-422/485
operation requires the use of two jumper blocks
inserted
in place of U17 and U16.
The
Jumper block needed for U17 connects pin 9 to pin 13, and
pin 14
to pin 15. The jumper block needed for
U16 connects pin
9 to
pin 10.
Circuit
Description
The
65C51 is memory mapped into four memory bytes starting at
address
$B5F8.
one of
the four set addresses is selected by the processor, the
74HC688's
generate a chip select to the 65C51. This signal is
also
coupled back on the VSC via diode D1 to the MEMDIS' pin.
The
IRQ' output is hooked directly to the interrupt INT' line on
the
VSC. The ACIA can provide real time
interrupts to the
processor
with this signal as conditions occur that require
processor
intervention, such as receive buffer full, or transmit
buffer
empty. It is an "open
collector" output that pulls down
the
pull up on the processor board.
The
RES' signal of the 65C51 is hooked to the RESET' line in the
VSC. The low voltage detector on the processor
should give a
power
up hardware reset to start the ACIA in a known state.
Also
the 65C51's R/W input is hooked to the R/W line.
The
R65C51 receives and transmits data serially and maintains
the
status of several control lines. The
serial data into the
65C51
comes either from the RS-232 interface as received and
translated
by the ICL232 (U16) and 145406 (U17), or from the
RS-422/RS-485
interface as received and translated by the
75176's
(U19 and U18).
The
ICL232 (U5) charge pump provides positive and negative
voltage
(+9V/-9V) to the RS-232 drivers. The
four capacitors,
C29
through C32, are used by the charge pump circuitry. The
ICL232
and the 145406 convert the signal
levels from the TTL
levels
of the ACIA to the RS-232 levels. The
ICL232 has two
RS-232
transceiver pairs. The 1454 06 further
augments the
drive
capability with its three transceiver pairs.
9 is the
RS-232
cable connection. Connector J10 is used
for RS-422/485
signa
Jumpers
"AA" and "BB" select whether a "two twisted pair"
RS-422
is to
be used, or a "single twisted pair" RS-485 instead. Jumper
"CC"
selects between RS-232 and RS-422/485.
With jumper "CC"
shorting
the left two pins, RS-422/485 is selected.
RS-422
operation
is then selected by shorting the left two pins on
jumper
blocks "AA" and "BB".
Shorting the right two pins on
these
blocks sets the RS-485 mode.
Registers
The
65C51 ACIA Device is assigned four addresses within the
processor
memory map. The specific register
addresses are
$B5F8,
$B5F9, $B5FA, and $B5FB. Note that the
system can read
from,
or write into the Command and Control registers, but the
65C51
will only allow reads of the Receiver Data Register.
Likewise,
it will only write the Transmitter Data
Register.
The
Status Register can be read, but not written.
A write to
the
Status Register location will for ce a reset of the 65C51.
ADDRESS READ WRITE
$B5F8
rcv data xmt data
$B5F9 status program
reset
$B5FA command command
$B5FB control control
COMMAND
REGISTER
PMC1
PMC0 Parity Mode Control
0 0 Odd parity
transmitted/received
0 1 Even
parity transmitted/received
1 0 Mark
parity transmitted, check disabled
1 1 Space
parity transmitted, check disabled
PME Parity Mode Enable
0 No parity bit
generated transmitting, no parity check
receiving
1 Parity mode enabled
REM Receiver Echo Mode
0 Receiver normal mode
1 Receiver echo mode
TIC1
TIC0 Transmitter Interrupt
Control
0 0 RTS' =
High, transmitter disabled
0 1 RTS' =
Low, transmitter interrupt enabled
1 0 RTS' =
Low, transmitter interrupt disabled
1 1 RTS' =
Low, transmitter interrupt disabled,
transmit break on TxD
IRD Receiver Interrupt Request Disable
0 IRQ' enabled (receiver)
1 IRQ' disabled (receiver)
DTR Data Terminal Ready
0 Data terminal not ready (DTR' high)
1 Data terminal ready (DTR' low)
CONTROL
REGISTER
SBN Stop Bit Number
0 1 stop bit
1 2 stop bits
1 1.5 stop bits, for WL=5 and no parity
1 1 stop bit, for WL=8 and parity
WL1
WL Word Length
0
0 8
0
1 7
1
0 6
1
1 5
RCS Receiver Clock Source
0 External receiver clock
1 Baud rate set by SBR3-SBR0
SBR3
SBR2 SBR1 SBR0
Selected Baud Rate for:
1.8432 3.6864 MHz xtal
TxC rate / 16 TxC rate / 16
0 0 0 0 50 100
0 0 1 0 75 150
0 0 1 1 109.92 219.84
0 1 0 0 134.58 269.16
0 1 0 1 150 300
0 1 1 0 300 600
0 1 1 1 600 1200
1 0 0 0 1200 2400
1 0 0 1 1800 3600
1
0 1 0
2400 4800
1 0 1 1 3600 7200
1 1 0 0 4800 9600
1 1 0 1 7200 14400
1 1 1 0 9600 19200
1 1 1 1 19200 38400
STATUS
REGISTER
bit
7 bit6 bit5 bit4 bit3
bit2 bit1 bit0
IRQ DSR'
DCD' TDRE RDRF
OVRN FE PE
IRQ Interrupt (IRQ)
0 No interrupt
1 Interrupt has occurred
DSR' Data Set Ready
0 DSR low (ready)
1 DSR high (not ready)
DCD' Data Carrier Detect
(DCD)
0 DCD low (ready)
1 DCD high (not ready)
TDRE Transmitter Data Register Empty
0 Not empty
1 Empty
RDRF
Receiver Data Register Full
0 Not full
1 Full
OVRN Overrun
0 No overrun
1 Overrun has occurred
FE Framing Error
0 No framing error
1 Framing error
detected
PE Parity Error
0 No parity error
1 Parity error detected
Programming
Writing
drivers for the 65C51 is not particulary difficult. The
following
discussion outlines issues concerning initialization,
enabling,
disabling, main line software and some miscellaneous
programming
notes.
Initialization
Software
The
ACIA initialization software must:
a. Execute a program reset (write operation
to the Status
Register
location, B5F8+1 to reset the Status, Control, and
Command
Registers to their initialization values).
Note that a
program
reset disables interrupts.
b. Set interrupt vectors to interrupt
handlers, if interrupts
are
used.
c. Write the initial values into the
Control and Command
Registers. This can enable operations immediately, or
leave
operations
disabled until another routine enables them.
Enable
Operations Software
If the
Initialization Software does not enable operations, a
routine
must be provided that enables (i.e., starts) either the
sending
or receiving operation, or both.
a. Set
the Command Register Bit 0 to "1" when the serial
channel
is to appear "ready" to the external device. Note: With
the
Command Register Bit 0 set to "1" the DCD (Data Carrier
Detect)
and DSR (Data Set Ready) interrupts are enabled.
b. Set the Command Register Bits 3 and 2 to
"01" when
Transmitter
Data Register Empty interrupts are enabled to the
processor,
and Request to Send (RTS) responses to the external
device
are to be enabled.
c. If
applicable, set the Command Register Bit 4 to a "1"
whenever
the echo mode is used. The Echo mode
can be used to
monitor
data transmitted from the ACIA module by feeding the
transmitted
data back to the processor via the Receive Data
Register.
Disable
Operations Software
If
operations are ever to be disabled, a routine must be
provided
that disables (i.e.: stops) either the sending or
receiving
operation, or both.
a. Set
the Command Register Bit 0 to "0" when the serial
channel
is to appear "not ready" to the external device. Note:
With
the Command Register Bit 0 set to "1" the DCD (Data
Carrier
Detect) and DSR (Data Set Ready) interrupts are disabled.
b. Set the Command Register Bit 1 to
"1" when Receiver Data
Register
Full interrupts to the processor are to be disabled.
c. Set Command Register Bits 3 and 2 to
10 or 11 when the
transmitter
interrupt is to be disabled but RTS (Request to
Send)
is to be left enabled. Bits 3 and 2 set
to 10 can be used
for
Data Set operations to indicate the ACIA will send, not
receive. Bits 3 and 2 set to 11 can be used to
disable Transmit
Data
Register Empty interrupts when a Break character is
transmitted
at the end of an output message.
Main-Line
Software
Because
of the special functions of the various Status Register
bits,
there is a suggested sequence for checking them. When an
interrupt
occurs, the ACIA should be interrogated as follows:
a. Read the Status Register. This automatically clears Bit 7
(IRQ). Subsequent transitions on DSR and DCD will
cause new
interrupts.
b. Check IRQ (Bit 7) in the data already
read from the Status
Register. If not set, the interrupt source is not the
ACIA.
c. Check DCD and DSR. These must be compared to their previous
levels,
which must have been saved by the processor.
If they
are
both 0 (modem "on-line") and they are unchanged, then the
remaining
bits must be checked.
d. Check the RDRF (Bit 3). Check for Receiver Data Register
Full.
e. Check Parity, Overrun, and Framing Error
(Bits 2-0). If the
Receiver
Data Register was full, check the validity of the
received
data and then accept it if correct.
f. Check TDRE (Bit 4). Check for Transmitter Data Register
Empty. If the Transmitter Data Register is empty,
provide the
next
character for transmission.
g. If
none of the above conditions exist, then CTS must have
gone to
the false (high) state.
Negative
logic Data Set Ready and Data Carrier Detect status are
indicated
by "1"s in bits 6 and 5, respectively, of the Status
Register. A status change on DSR or DCD
unconditionally sets
the
interrupt flag (bit 7) of the Status Register to a "1" which
generates
an interrupt if bit 0 of the Command Register is a "1".
A
Transmitter Data Register Empty
condition is indicated by bit
4 of
the ACIA Status Register. Providing the
ACIA Command
Register
has been programmed to a transmit interrupt enable
state
(bits 3 and 2 = 01), a Transmit Data Register Empty
condition
sets the Interrupt Flag (bit 7) in the Status Register
to a
"1".
A
Receiver Data Register Full condition is stored as a "1" in
bit 3
of the ACIA Status Register. Providing
the ACIA Command
Register
has been programmed to a receiver interrupt enable
state (bit
1 = 0), a Receiver Data Register Full condition sets
the
Interrupt Flag (bit 7) in the Status Register to a "1".
Programming
Notes
The
ACIA can operate in full-duplex mode or half-duplex mode.
In
full-duplex mode data can be simultaneously transmitted to
and
received from an external device. In
this case, software
must
handle Transmitter Data Register Empty interrupts that are
interleaved
with Receiver Data Register Full interrupts.
In the
half-duplex
operation, system software receives non-interleaved,
successive,
Transmit Data Register Empty throughout the duration
of a
complete output message, or non-interleaved, successive,
Receive
Data Register Full interrupts throughout the duration of
a
complete input message.
An
external RS-232 device may require a true CTS (Clear to Send)
signal
before it transmits data to the ACIA.
The true CTS
signal
notifies the external device that the ACIA is ready to
receive
data. For Data Set operation, CTS is
produced from an
RTS
(Request to Send) output from the ACIA.
The RTS signal is
generated
by programming bits 3 and 2 in the ACIA Command
Register. If the system application allows the ACIA to
always
appear
ready to receive data, RTS can be programmed to the CTS
enable
state during system initialization and left that way.
With
RTS programmed to a constant enable state, transmit
interrupts
are operational and can be included in I/O processing.
For
Data Set operations, it may not be desirable to have the
ACIA
port appear ready to receive data at all times. In this
case,
Command Register bits 3 and 2 must be periodically
programmed
to the RTS disabled state (RTS high).
Disabling RTS
also
disables Transmit Data Register Empty interrupts. Thus in
full-duplex
Data Set applications where RTS is periodically
enabled
and disabled, the software can not rely on transmit
interrupts,
but must routinely read the Status Register to
detect
Transmitter Data Register Empty status.
For
RS-232 half-duplex Data Set operations, data is never
transmitted
or received simultaneously. In this
case, the RTS
signal
can be set high when the ACIA channel is to appear "not
ready"
to receive data, and set low when the ACIA is
transmitting
data and therefore requires Transmitter Data
Register
Empty interrupts. This works because
the remote
transmitter
will not send while the ACIA is sending.
Test
software
For
RS-232 you can do RTS handshaking; when you set RTS high you
warn
the remote transmitter not to send.
(Some remote systems
will
ignore your RTS line. The NMIX boards
have an RS-232 line
that
ignores RTS, for example.) By setting
RTS low only when
you're
ready to receive, you can do error-free RS-232
communication
without interrupts, although the throughput will
not be
high.
Real
Time Interrupts
Interupts
can be useful when very high transfer rates of serial
data
are desired with continuing foreground operations happening
"simultaneously".
CODE-SUB
CLI
0E C, ( CLI
39 C, ( RTS
END-CODE
CODE-SUB
SEI
0F C, ( SEI
39 C, ( RTS
END-CODE
CODE-SUB
CLS
07 C, ( TPA
84 C, 7F C, ( ANDA # 7F
06 C, ( TAP
39 C, ( RTS
END-CODE
CODE-SUB
STOP
CF C, ( STOP
39 C, ( RTS
END-CODE
CODE-SUB
ACIA-IRQ
3B C, ( RTI
END-CODE
VARIABLE
VEC-TABLE -2 ALLOT
7E C,
FFFE @ , ( B7BF SCI SER SYS )
7E C,
FFFE @ , ( B7C2 SPI SER )
7E C,
FFFE @ , ( B7C5 PLS ACC OVFL )
7E C,
FFFE @ , ( B7C8 PLS ACC EDGE )
7E C,
FFFE @ , ( B7CB TMR OVERFLOW )
7E C,
FFFE @ , ( B7CE TMR OUT CMP 5 )
7E C,
FFFE @ , ( B7D1 TMR OUT CMP 4 )
7E C,
FFFE @ , ( B7D4 TMR OUT CMP 3 )
7E C,
FFFE @ , ( B7D7 TMR OUT CMP 2 )
7E C,
FFFE @ , ( B7DA TMR OUT CMP 1 )
7E C,
FFFE @ , ( B7DD TMR IN CAP 3 )
7E C,
FFFE @ , ( B7E0 TMR IN CAP 2 )
7E C,
FFFE @ , ( B7E3 TMR IN CAP 1 )
7E C,
FFFE @ , ( B7E6 REAL TIME )
7E C, '
ACIA-IRQ @ , ( B7E9 IRQ )
7E C,
FFFE @ , ( B7EC XIRQ )
7E C,
FFFE @ , ( B7EF SWI )
7E C,
FFFE @ , ( B7F2 OP-CODE TRAP )
7E C,
FFFE @ , ( B7F5 COP FAILURE )
7E C,
FFFE @ , ( B7F8 CLK MON )
HERE
CONSTANT VEC-TABLE-END
:
VEC-INIT
( CHECK
AND MOVE VECTORS IF NECESSARY )
VEC-TABLE-END VEC-TABLE - 0 ( RANGE )
DO
B7BF I + C@ VEC-TABLE I + C@ = NOT
IF VEC-TABLE I + C@ B7BF I + ."
." EEC! THEN
LOOP
;
:
ENABLE
SEI
VEC-INIT
CLI
;
Program
Segments
COLD
HEX
( setup
registers, basic requirements )
8000 CONSTANT
BASE-ADDR ( set region of
memory once)
0
BASE-ADDR + CONSTANT DATA
1
BASE-ADDR + CONSTANT STATUS
2
BASE-ADDR + CONSTANT COMMAND
3
BASE-ADDR + CONSTANT CONTROL
: INIT
( control command -- )
0 STATUS C! ( program reset )
COMMAND
C! ( set command register )
CONTROL
C! ( set control register )
;
:
TDREADY? STATUS C@ 10 AND ; ( check if
you can send )
:
RDREADY? STATUS C@ 08 AND ; ( check if
you've received )
:
S-EMIT ( char -- )
BEGIN TDREADY? UNTIL ( wait till last char
is done)
DATA C! ( send next char )
;
: S-KEY
( -- char )
BEGIN RDREADY? UNTIL ( wait till a char is
here )
DATA C@ ( get it )
;
: S-?TERMINAL
RDREADY? ; ( is a char here now?
)
:
S-TYPE ( ca -- ) ( send a
string )
COUNT ?DUP IF
( ca+1
n ) 0 DO
( ca+i
) COUNT S-EMIT LOOP
THEN
( ca+i
) DROP
;
:
~S-CR? ( char -- char 0 | 1 )
DUP 0D = IF SPACE 0 ELSE DROP 1 THEN ;
: S-BS
( ca ca+i -- ca f )
OVER SWAP U< IF
8 EMIT THEN 0 ;
:
S-CHAR?
( ca+u ca' char -- ca+u ca'+1 f )
( ca+u
ca' char ) DUP EMIT ( display char )
( ca+u
ca' char ) OVER C! ( save char in buffer )
( ca+u
ca' ) 1+ ( bump pointer )
( ca+u
ca'+1 ) 2DUP U< ; ( buffer full? )
:
S-EXPECT ( ca +n -- ) ( accepts remote string )
( stores at
address ca )
( no more than +n
chars, not counting )
( those that were
backspaced )
( echoes string to
terminal )
( ca u
) OVER + OVER
( ca
ca+u ca) BEGIN
( ca
ca+u ca+i) S-KEY ~S-CR? IF
DUP 7F = IF ( funny backspace char? )
DROP S-BS ( backspace )
ELSE S-CHAR? ( or handle
char )
THEN
THEN
UNTIL 2DROP DROP ( quit if CR or buffer full )
;
(
debugging commands )
:
.STATUS ( reports status register )
STATUS C@
DUP 80 AND IF ." Interrupt " CR
THEN
DUP 40 AND IF ." DSR High (not
ready)" CR THEN
DUP 20 AND IF ." DCD High ( not
ready)" CR THEN
DUP 10 AND 0= IF ." Transmitter not
empty" CR THEN
DUP
8 AND IF ." Receiver full" CR THEN
DUP
4 AND IF ." Overrun" CR THEN
DUP
2 AND IF ." Framing error" CR THEN
1 AND IF ." Parity error" CR
THEN ;
:
PARITY-TYPE ( x -- )( used by another routine to report parity)
DUP 0C0 AND
DUP
0= IF ." Odd parity set" THEN
DUP 40 = IF ." Even parity set"
THEN
DUP 80 = IF ." Mark parity set, no
checking" THEN
0C0 = IF ." Space parity set, no
checking" THEN CR
;
: .RTS
( x -- ) ( used by another routine to report RTS setting)
DUP 0C AND
DUP
0= IF ." RTS high, transmitter disabled" THEN
DUP 4 = IF ." RTS low, transmitter interrupt enabled" THEN
DUP 8 = IF ." RTS low, transmitter interrupt disabled" THEN
0C = IF ." RTS low, transmitter interrupt disabled" THEN
CR
;
:
.COMMAND ( reports Command Register
)
COMMAND C@
DUP 20 AND IF PARITY-TYPE ELSE
." Parity mode disabled, no parity
sent, no checking" CR
THEN
DUP 10 AND IF ." Receiver echoes"
CR THEN
.RTS
DUP 2 AND IF ." Receiver interrupt
request disabled" ELSE
." Receiver interrupt request
enabled" THEN CR
1 AND IF ." DTR low, ready"
ELSE ." DTR high, not ready"
THEN CR
;
: 8BITS-PAR
( cmd -- cmd f ) ( subroutine to report stop bits )
DUP 60 AND 0= COMMAND C@ 20 AND AND DUP IF
." 1 stop bit" THEN ;
:
5BITS-NO-PAR ( cmd -- cmd f )( subroutine to report stop bits )
DUP 60 AND 60 = COMMAND C@ 20 AND 0= AND
DUP IF
." 1.5 stop bits" THEN ;
:
.STOPBITS ( cmd -- cmd ) (
subroutine to report stop bits)
DUP 80 AND 0= IF ." one stop bit"
ELSE
8BITS-PAR 0= IF 5BITS-NO-PAR 0= IF ."
2 stop bits" THEN THEN
THEN CR ;
CREATE
BAUDS DECIMAL
0 ,
100 , 150 , 220 ,
269 , 300 , 600 , 1200 ,
2400 ,
3600 , 4800 , 7200 , 9600 , 14400 , 19200 , 38400 ,
HEX
: #BITS
( x -- n ) ( subroutine to report
bits/char )
60 AND >< 2/
( 0-3 )
8 SWAP -
( 5-8 )
. ." bits" CR ;
:
.CONTROL ( reports
Control Register )
CONTROL C@
8 OVER 60 AND >< 2/ - . ." bits" CR .STOPBITS
DUP 10 AND 0= IF ." external
clock" ELSE
0F AND 2* BAUDS + @ U. ." Baud"
THEN CR ;
:
.? ( reports all registers )
.COMMAND .CONTROL .STATUS ;
( for
testing )
:
TEST-SEND ( send a test
pattern )
17 0B INIT .?
BEGIN
FE 20 DO
BEGIN TDREADY? UNTIL ( wait til transmitter ready)
I DATA C! ( send new char )
200 0 DO LOOP ( wait in case remote is slow )
LOOP
0 UNTIL ; ( repeat til push reset button)
:
TEST-GET1 ( receive with no RTS handshaking )
( RTS low )
17 0B INIT
BEGIN
BEGIN RD-READY? UNTIL
DATA C@ EMIT ( get char )
?TERMINAL ( stop if keypress )
UNTIL KEY DROP ;
:
TEST-GET2 ( receive with RTS
handshaking )
( for RS-232 )
17 0B INIT
BEGIN
COMMAND C@ 8 OR COMMAND C! ( RTS low )
BEGIN RD-READY? UNTIL
03 COMMAND C! ( RTS high )
DATA C@ EMIT ( get char )
?TERMINAL ( stop if keypress )
UNTIL KEY DROP ;
:
TEST-FULL ( send and
receive both )
17 0B INIT ( full-duplex RS-232 or RS-422)
BEGIN
FE 20 DO
RDREADY? IF
DATA C@ EMIT THEN ( get char if char is received)
BEGIN TDREADY? UNTIL ( wait til transmitter ready )
I
DATA C! ( send char )
100 0 DO LOOP ( wait in case remote is slow )
LOOP
0 UNTIL ;
:
TEST-GET3 ( receive with no
RTS handshaking )
( RTS high )
17 03 INIT
BEGIN
BEGIN RD-READY? UNTIL
DATA C@ EMIT ( get char )
?TERMINAL ( stop if keypress )
UNTIL KEY DROP ;
AC
POWER SUPPLY
The
power supply circuit on the NMIX-0020-S1 is designed to
allow
the board to operate from a
simple, low-voltage, AC
walltransformer. It has three major sub
circuits -
rectification,
regulation and DC to DC conversion.
Battery
backup
capabilities are also provided to the 28 pin JEDEC
sockets
and the F68HC11 internal RAM, and a power-up power-down
reset
circuit.
Connection J2
is for AC (9VAC) voltage input or for DC
voltages
greater than 8 volts to be input.
The
bridge rectifier converts the AC to DC.
The 7805
regulates
this rectified incoming voltage to a constant 5 Volts.
The upper
limit of +V is set by the ability of the 7805 to
dissipate
heat. If a heat sink is added to the
7805, voltages
in excess
of 20 Volts are possible.
Driving the 7805 too
hard,
however, will cause it to enter thermal
overload and
"shut
down" its output.
The typical
current required by the
NMIX-0020-S1 with 8K CMOS
RAM and
the Max-FORTH ROM at 2 Mhz from 9 VAC is 60mA.
The
ICL232 RS-232 interface chip generates its own + and - V
for
RS-232 levels. A
multiple stage charge pump produces
+9V
and -9V. The negative output is also used to get the
negative
voltage bias for the LCD display to increase contrast.
DC POWER,
BATTERY BACK UP, AND RESET
Connection
J3 provides a means to connect an external +5VDC
power
source or to access the on board +5VDC supply if the AC
power
connector is providing board power.
Other connections on
J3
provide access to VBB and Ground.
The battery backup capability allows data
retention in
otherwise
volatile CMOS RAMs and the processor's own internal
RAM through main-board power-downs. A third terminal on the
power
connector, J3, is marked VBB for Voltage Battery Backup.
The VBB
terminal on J3 is connected to the VBB supply rail on
the
board by diode, D1.
The VBB supply rail supplied the
three
28 pin JEDEC sockets, the 8054HN low
voltage indicator in
the
reset circuit (Rev A), one 74HC00 gate
and the 74HC138
decoder. If no power is applied to the VBB
terminal, the VBB
rail is
supplied through a P channel FET,
Q1, to within a
diode
drop of the supplying 5 volt rail (~4.4 Volts). When the
8054HN
low voltage indicator releases the
reset line, Q1 is
turned
on and the VBB comes almost completely up to the 5 volt
rail
(~4.95 Volts). (This may cause some problem with the
Dallas
Semiconductor DS1223
battery sockets,
as they "write
protect" their RAMs at
4.75
Volts. Running an elevated 5 Volt
supply may be necessary
to
accommodate these parts. The purpose
of this feature is,
however, to
do away with
the need for
those devices in
final
system configurations.)
When
the 8054HN low voltage indicator holds the
reset line
low (when
VBB is below 3.8-4.2 Volts, Rev
A), Q1 is turned
off
and the address decoder is disabled
through the same input
that
is used by MEMDIS.
This "access" protects the
memories
during the power down cycle.
To meet
the full letter of the specifications of
the parts
involved the
correct backup voltage on the VBB pin is
critical. This supply must be low enough to
ensure that after
the
diode
drop of
D1, the VBB rail cause the 8054HN to
issue a reset
(~4.0
Volts), otherwise Q1 will remain on and
the whole system
will be
powered by VBB. It must also be high
enough to ensure
that
after the diode drop of D1, the VBB rail will meet the
processors
required backup voltage (listed as
4.0 Volts).
Therefore, the ideal voltage for the VBB supply is
4.3-4.5
Volts. It should be pointed out, however,
the Motorola
specification
appears to be overly conservative. By
empirical
test, VBB supplies below 3 Volts appear
to be quite
adequate. Most CMOS RAMs will retain data down to
2.2 Volts.
Accounting for the diode drop under such low currents, the VBB
supply
may work as low as 2.5 Volts.
The
processor battery backup supply enters the chip via the MODB
pin. Jumper
block D controls the setting of
MODB, either
to
ground or to VBB. For backup of the
processor's RAM to be
successful jumpers
D and E must be in the Single
Chip or
Expanded
Multiplexed settings. When the VBB
supply is used on
the
processor, it will retain its User Area through power down
and
remember its linkages to the external FORTH dictionary.
ADDRESS
DECODING
The
chip selects of the three JEDEC sockets are
generated by
a
74HC138. When jumpers A and B are in
the 8K position,
address
lines A15 to A13 are brought to this part.
This means
that
each of the eight generated chip
selects represent a
single
8K byte segment out of the 64K byte memory map.
When
jumpers A and B are in the 16K position,
address lines
A15
and A14 are brought to this part. The A13 is held high.
This
means that the upper four
generated chip selects
represent a single 16K byte segment out of the 64K
byte memory
map.
When jumpers A and B are in the 32K
position, address line A15
alone
controls the part. The A14 and A13 are
held high.
This
means that each of the two upper chip selects represent
a 32K
byte segment out of the 64K byte memory map.
Two
other signals control the decoder - Address Strobe (AS')
and On
Board Memory Disable (MEMDIS'). The
Address Strobe (AS')
signal
must be active low before any chip selects are enabled.
This
is the
processor's signal indicating
the address on the
bus is
valid for the off-chip memory.
The On Board Memory
Disable
(MEMDIS') signal allows an off-board open collector
source
to disable the on
board decoder, so offboard
components
can usurp a memory segment from
on-board memory,
even if the entire 64K is filled with RAM on
the main board.
74HC138
+5V
A A13 +----u----+ C
o o o --|A Vcc|-+5V +------+
+5V
B A14 | | | |
o o o --|B O0|-O0---|
o o |-+-U2 CHIP SELECT
| | |
| |
A15-|C O1|-O1---| o o |-+
__ |_ | |
| |
AS-|E O2|-O2---|
o o |-+
MEMDIS'|_ | |
| |
+ -|E O3|-O3---|
o o |-+
RESET'| | |
| |
E-|E O4|-O4---| o o |-+
| | |
| ______________
+---O7-|O7 O5|-O5---| o o |-+-U3 CHIP SELECT
| | | | | |
| GND-|GND O6|-O6---| o o |-+
| +---------+ |
| _________
+-----------------------| o o
|---U4 CHIP SELECT
+------+
TROUBLESHOOTING
As always the first thing to do when
troubleshooting is to
check
the power and ground connections. An
oscilloscope should
be used
to check signals. The heat sink of
the 7805 is a
convenient
place to hook a ground clip. If
+5 Volts is
present
at J3 and the board is not operational, the next item to
check
is the oscillator. Putting the scope
on EXTAL (Pin 7)
should
show a 8 Mhz sine wave (4 Mhz F68HC11 parts running 4
Mhz
XTAL's) running from about .5 Volt
lows to 4.5 Volt
peaks. XTAL (F68HC11 Pin 8) should have an
identical signal,
but of
a much smaller amplitude. If the sine
waves are not
present and there is 5V present at the power pin Vcc
(Pins 26),
and
ground at Vss (Pin 52), then either
the F68HC11 or the
crystal are
bad and require replacement.
There is one
exception. If the processor has executed a STOP
instruction,
the
oscillator will stop. When the
oscillator is
functioning correctly
a 2 Mhz (1 Mhz) clean running square
wave
should be present at the E output (Pin 5).
The E signal
drives
the
timing for all external memory transfers.
This signal
should
transition nearly rail to rail, a 0.4V low and a 4.6V
high
are normal. Less amplitude can
indicate a board short or
an excessive load on the line external to the
F68HC11.
The serial channel should send a sign on message
if no
autostart
ROM interferes. If not, the reset circuit could be
bad,
the serial converter could have failed, or the F68HC11
could
be defective. With the
reset button depressed the
RES pin
(Pin 17) should be at ground. When
released, the pin
should
rise to 5 Volts. If the reset
pin is working and
still
no message is seen
on the
terminal, check PD1, the serial output line (Pin
21). When
reset is exercised, this line
should go from
normally
high through a multitude of toggles back to a high
state. The periods of the toggle transitions are
multiples
of approximately 100 microseconds. If
this signal is not
present, and there are no user ROMs in the board, the
F68HC11
is
suspect. If the signal is present,
check pin 3 of the DB25F
connector. It should normally be at
-V (-9 Volts nominally)
and
should toggle to +V (+9 Volts nominally) at the same rate as
the
serial output line. If this is happening and no message
is
seen, the RS-232 wiring or the terminal
is suspect. Check
to see
if J1 is connected to the DB25F RS-232
connector as
follows:
DB9F DB25F Signal Name
---- ----- ------ ----
1 Case ground
2 2 Serial in to SBC
3 3 Serial out from SBC
5 7 Electrical ground
7 to 8 4 to 5 CTS to RTS
4 to 6 6 to 20 DSR to DTR
Check
the voltages on pins 2 and 3. If pin 3 is very negative
and pin
2 is floating, both systems are trying
to talk on the
same
line. Pins 2 and 3 need to be swapped.
Usually this
is done
with a "null modem" inserted where the two systems
connect.
If the
-V/+V signal was not found at pin 3,
the RS-232
converter
is not
working. Check pin 2 of the
ICL232 for +V
and pin
6 of the ICL232 for -V. If these
signals are not
present, the charge pump of the ICL232 has
failed. Pin 14 of
the
ICL232, the output, should look the same as pin 3 of J1.
Check
pin 2 of J1 which is the serial into the board from the
terminal. It
should normally be at a negative voltage
between
-3 and -15 Volts. When a key is
pressed on the
terminal
it should pulse to positive
voltages between +3
and +15
Volts. If it doesn't, the terminal or
the RS-232
wiring
are suspect. The same signals at
inverted TTL levels,
should
also be at PD0, which is the serial
input line of the
processor
(Pin 20).
The most
common error in
trying to use the NMIX-0020-S1 is
mismatched
baud rates or bit settings. Verify
that the
terminal
is set for 9600 baud with one start
bit, eighth
data
bits and one stop bits, with no parity generated. If using
Forth, be sure to use CAPITALS. (Review this discussion in
the
Getting Started section.)
MEMORY
MAP
K# HEX
-- -----
64 $FFFF +------------+
63 | RUN TIME |
62 | KERNEL |
61 | |
60 |NON RUN TIME| Max-FORTH ROM
59 | CODES |
58 | |
57 | HEADS |
56 $E000 |____________|
$DFFF | V3.5
|
|
FLOATING |
|
POINT |
$D000 |____________|
$CFFF | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
$B800 |____________|
$B600 |____________|
EEPROM
$B5FC |------------|
LCD
$B5F8 |------------|
ACIA
$B00A |------------|
KEYBOARD
$B000 |============|
REGISTERS
| |
| |
~ ~
~ ~
| |
| |
5 | |
4 $1000 |$0B_AT_$103B|
3 $C000 |
|
2 $0800 |
|
1 $0400 |
|
0 $0000 +ON=CHIP=RAM=+
MISCELLANEOUS
JUMPERS
SOURCE DESTINATION NORMALLY
------------------ ----------------------- --------
A
A13-A
ADDRESS LINE 13 ADDRESS
DECODER INPUT
A-5
+5 VOLT RAIL
B
A13-A
ADDRESS LINE 13 ADDRESS
DECODER INPUT
A-5
+5 VOLT RAIL
C
O0-U2
DECODER OUTPUT 0 U2 JEDEC
SOCKET
O1-U2
DECODER OUTPUT 1 U2 JEDEC
SOCKET
O2-U2
DECODER OUTPUT 2 U2 JEDEC
SOCKET
O3-U2
DECODER OUTPUT 3 U2 JEDEC
SOCKET
O4-U2
DECODER OUTPUT 4 U2 JEDEC
SOCKET
O5-U3
DECODER OUTPUT 5 U3 JEDEC
SOCKET
O6-U3
DECODER OUTPUT 6 U3 JEDEC
SOCKET
O7-U4
DECODER OUTPUT 7 U4 JEDEC
SOCKET
D
GND-D
GROUND MODB PIN OPEN
D-5
MODB PIN +5 VOLT
RAIL CLOSED
E
GND-E
GROUND MODA PIN OPEN
E-5
MODA PIN +5 VOLT
RAIL CLOSED
F
XIRQ-F
XIRQ' INT FROM J4 OPEN
F-IRQ
IRQ' INT FROM
J4 OPEN
G
485-G
PA3 U12 PINS 2
& 3
G-422
U12 PINS 2 & 3 GROUND
H
U2
U2 PIN 27 R/W LINE U2 PIN 28
SUPPLY OPEN*
I
U3
U3 PIN 27 R/W LINE U3 PIN 28
SUPPLY OPEN*
J
U4
U4 PIN 27 R/W LINE U4 PIN 28
SUPPLY OPEN*
K
232-K
U6-PIN9 CLOSED
K-422
U10-PIN1
OPEN
L,M NOT USED
N,O,P SEE SECTION ON SETTING MEMORY JUMPERS
AA
PA7-AA
PA7 U19 PINS
2&4 OPEN
AA- +5V AA ENABLE OPEN
BB
PA7-BB
PA7 U18 PINS 2&4 OPEN
BB-GND OPEN
CC
RXD-CC U15 PIN 12
U16 PIN 12 CLOSED
CC-RO U16 PIN 12
U18 PIN 1 OPEN
* Option of pullups on R/W lines to write
protect
RAMs in socket. To use install 100K pullup resistor & remove
jumper from 28 pin JEDEC selection socket
for pin 27.
If battery backup is in use, RAM will then
emulate ROM.
GENERAL
PURPOSE SOCKETS
Jumper Assignments for JEDEC 28 Pin Sockets
+---+
JUMPER
1 o o 28
+5 | o |
| |
*
A12 2 o o 27 JUMPER | o |
+---+
A7 3 o o 26 JUMPER
A6 4 o o 25 A8
A5 5 o o 24 A9
A4 6 o o 23 A11
A3 7 o o 22 OE
A2 8 o o 21 A10
____________
A1 9 o o 20 CHIP SELECT
A0 10 o o 19
D7
D0 11 o o 18
D6
D1 12 o o 17
D5
D2 13 o o 16
D4
GND 14 o
o 15 D3
PIN 1 PIN 26 PIN 27
O---O O---O O---O
O
O O O O O
A14 +5 +5 A13 A14 RR/W
* Option of pullups on R/W lines to write
protect RAMs in
socket.
To use, install 100K pullup resister & remove
jumper For pin 27. If battery backup is in
use, RAM will
then emulate ROM.
SOCKET
JUMPER SETTINGS
GENERAL PURPOSE SOCKET - U6, U7, U8
Jumper Settings for Standard JEDEC 24/28 Pin
Devices
ALL 8K X 8 DEVICES
2764, 2864, 6264
PIN 1 PIN 26 PIN 27
+---+---+---+---+---+---+
| | X | X | |
| X | *
| | X | X | |
| X |
+---+---+---+---+---+---+
A14 +5V +5V A13 A14 RR/W
16K X 8 EPROM
27128
PIN 1 PIN 26 PIN 27
+---+---+---+---+---+---+
| | X | | X |
| X |
| | X | | X |
| X |
+---+---+---+---+---+---+
A14 +5V +5V A13 A14 RR/W
32K X 8 EPROM
27256
PIN 1 PIN 26 PIN 27
+---+---+---+---+---+---+
| | X | | X | X |
|
| | X | | X | X |
|
+---+---+---+---+---+---+
A14 +5V +5V A13 A14 RR/W
32K X 8 RAM
62256
PIN 1 PIN 26 PIN 27
+---+---+---+---+---+---+
| X | | | X |
| X | *
| X | | | X |
| X |
+---+---+---+---+---+---+
A14 +5V +5V A13 A14 RR/W
*
Rev 2.x has option of pullups on R/W lines to write
protect
RAMs in socket. To use, install 100K
pullup resistor &
remove
jumper for pin 27. If battery backup is
in use, RAM will
then
emulate ROM.
Jumper Settings for Various Addressing Schemes
3 8K DEVICES
+5V A A13
+---------+
| o XXXX |
+---------+ 8K POSITION
| o XXXX |
+---------+
+5V B A14
C
+------+
___________ 0000
0000-1FFF O0 | XXXX |-+-U2 CHIP SELECT ----
| | | 1FFF
2000-3FFF O1 | o o |-+
| | |
4000-5FFF O2 | o o |-+
| | |
6000-7FFF O3 | o o |-+
| | |
8000-9FFF O4 | o o |-+
| | ___________ C000
A000-BFFF O5 | o o |-+-U3 CHIP
SELECT ----
| | | DFFF
C000-DFFF O6 | XXXX |-+
| | ___________ E000
E000-FFFF O7 | *--* |---U4 CHIP SELECT ----
+------+
FFFF
3 16K DEVICES
+5V A A13
+---------+
| XXXX o |
+---------+ 16K POSITION
| o XXXX |
+---------+
+5V B A14
C
+------+
O0 | o o |-+
| | | ___________ 0000
0000-3FFF O1 | XXXX |-+-U2 CHIP SELECT
----
| | | 3FFF
O2 | o o |-+
| | |
4000-7FFF O3 | o o |-+
| | |
O4 | o o |-+
| | ___________ 8000
8000-BFFF O5 | XXXX |-+-U3 CHIP SELECT
----
| | | BFFF
O6 | o o |-+
| | ___________ C000
C000-FFFF O7 | *--* |---U4 CHIP SELECT ----
+------+
FFFF
2 32K DEVICES
+5V A A13
+---------+
| XXXX o |
+---------+ 32K POSITION
| XXXX o |
+---------+
+5V B A14
C
+------+
O0 | o o |-+
| | |
O1 | o o |-+
| | |
O2 | o o |-+
| | | ___________ 0000
0000-7FFF O3 | XXXX |-+-U2 CHIP SELECT ----
| | | 7FFF
O4 | o o |-+
| | ___________
O5 | o o |-+-U3 CHIP
SELECT ----
| | |
O6 | o o |-+
| | ___________ 8000
8000-FFFF O7 | *--* |---U4 CHIP SELECT ----
+------+
FFFF
INPUT/OUTPUT
JACKS
SERIAL INPUT/OUTPUT JACK J6
TOP VIEW
NUMBERED LEFT TO RIGHT
1 2 3
4 5 6 7 8 9
10 11 12 13 14
----------------------------------------
o o o
o o o o o
o o o o o o
DB25F
J6 Signal Name
----- ---
-----------------------------
1
Spare RS-232 in
2 Spare RS-232 out
3 Spare TTL receiver out
4 Spare TTL transmitter in
1 5 Case ground
2 6 Serial into NMIX-0020-S1
3 7 Serial out of NMIX-0020-S1
7 8 Electrical ground
9 Reset line in or out
10 Electrical ground
11 RS-422 Receive +
Differential input or 485 xcv
12 RS-422 Receive -
Differential input or 485 xcv
13 RS-422 Receive + Differential
output
14 RS-422 Receive -
Differential output
INPUT/OUTPUT JACK J9
PIN 1 ------->RX2 o o RX1
R1I o o T2O
T1O o o R2I
TX1 o o N.C.
GND o o N.C.
INPUT/OUTPUT JACK J10
PIN 1 ------->GND o o -422T
N.C.o o N.C.
+422R/+485X o o N.C.
+422T o o -422R/-485X
N.C.o o N.C.
INPUT/OUTPUT JACK J5
TOP VIEW
FRONT (EDGE) OF CARD v
- X PD5 o o PD4 X
| X PD3 o o PD2 X
| X PD1 o o PD0 X
|
+5 o o +5
|
GND o o GND
| X PA7 o o PA6 O
| O PA5 o o PA4 O
34 pin header | X PA3 o o PA2 I
group | I PA1 o o PA0 I
|
+5 o o +5
|
GND o o GND
| I PE7 o o PE6 I
| I PE5 o o PE4 I
| I PE3 o o PE2 I
| I PE1 o o PE0 I
|
+5 o o +5
-
GND o o GND
I=INPUT O=OUTPUT X=EITHER
LCD DISPLAY JACK J1
TOP VIEW
FRONT (EDGE) OF CARD v
-
+5 o o GND
|
A0 o o Vo
|
E1 o o R/W'
16 pin header | D1 o o D0
group | D3 o o D2
|
D5 o o D4
|
D7 o o D6
-
E2 o o
KEYBOARD JACK J7
TOP VIEW
FRONT (EDGE) OF CARD v
J1 J7
- o o
P o Y1
|
o o N o Y2
|
o o M o X3
9 pin single- | o o
L o X2
inline-header | o o
K o Y3
behind J1 | o o
J o X1
|
o o H o X4
|
o o G o Y4
- F o Y5
VSC34 EXPANSION JACK J4
MEMDIS o o N.C.
E o
o RST
A15 o
o INT
A14 o
o +5
A12 o
o R/W
A7 o
o A13
A6 o
o A8
A5 o
o A9
A4 o
o A11
A3 o
o OE
A2 o
o A10
A1 o
o AS
A0 o
o D7
D0 o
o D6
D1 o
o D5
D2 o
o D4
GND o
o D3
The J4
expansion connector was designed to follow the JEDEC standard-
for
byte sized memory parts in the
8, 16 and 32K Byte
varieties.
The J4
connector on these boards are made to most closely match the
more
recently available 32K JEDEC parts.
PROGRAM
SEGMENTS
COLD
FORGET TASK
HEX
100 1C ! ( V3.3 ONLY!
50 1E ! ( V3.3 ONLY!
400 DP !
(**********************************************************
)
(LCD DISPLAY ROUTINES )
(**********************************************************
)
:
IS CONSTANT ;
B5FC IS DSP-CMD
B5FD IS DSP-DATA
:
WAIT-NOT-BUSY BEGIN DSP-CMD C@ 80 AND 0= UNTIL ;
:
CLEAR WAIT-NOT-BUSY 1 DSP-CMD C! ;
:
HOME WAIT-NOT-BUSY 2 DSP-CMD C! ;
:
CRLF WAIT-NOT-BUSY C0 DSP-CMD C! ;
:
MOVE-CURSOR WAIT-NOT-BUSY 80 OR DSP-CMD C! ;
:
RIGHT-UPPER-CORNER 27 MOVE-CURSOR ;
:
CURSOR? WAIT-NOT-BUSY DSP-CMD C@ 7F AND ;
:
DSP>L WAIT-NOT-BUSY 10 DSP-CMD C! CURSOR? 27 >
IF RIGHT-UPPER-CORNER THEN ;
:
DSP>R WAIT-NOT-BUSY 14 DSP-CMD C! CURSOR? 27 >
IF HOME THEN ;
:
DSP-EMIT WAIT-NOT-BUSY DSP-DATA C! ;
:
DSP-TYPE
BEGIN
DUP 0= NOT
WHILE
1- SWAP DUP C@ DSP-EMIT 1+ SWAP
REPEAT
2DROP
;
:
DSP-SPACE BL DSP-EMIT ;
:
DSP-SPACES 0 MAX BEGIN ?DUP WHILE 1- DSP-SPACE
REPEAT ;
:
DSP-ON
WAIT-NOT-BUSY
38 DSP-CMD C! ( GET ATTN
38 DSP-CMD C! ( SET 2 LINE DISP )
6 DSP-CMD C! ( CHARACTER ENTRY RIGHT )
E DSP-CMD C! ( DISPLAY CONTROL ON, CURSOR ON )
;
(**************************************************** )
(
KEYPAD ROUTINES )
(***************************************************
)
B00A IS KEYPAD
:
KP-?TERMINAL B000 C@ 1 AND ;
:
KP-KEY
BEGIN
KP-?TERMINAL
UNTIL
KEYPAD C@ 2/ 2/ 2/
;
:
KP-EXPECT
0 SPAN ! DUP
IF
OVER + OVER
BEGIN
-KEY DUP 0D ( OR DEFINE ENTER KEY INSTEAD OF 0D) =
IF
DROP SPACE 1
ELSE
DUP 08 ( OR DEFINE BACKSPACE KEY INSTEAD OF 08 ) =
IF
DROP 2 PICK OVER U<
IF
SPAN 1-! 1- 08 DUP EMIT SPACE EMIT
THEN
0
ELSE
2DUP SWAP C! EMIT
SPAN 1+!
1+
2DUP =
THEN
THEN
UNTIL
DROP
THEN
TDROP
;
NMIX-0020-S1
PARTS LIST
F68HC11 NMIX-0020-S1 PARTS LIST
REV 1.0
REF.DES. VALUE COMPONENT
--------------- -------------- -------------------------
C1,C4-6,
C13-20, .1UF CAPACITOR, MONO.
C22,C24-26,C33
C9-12,
C29-32 10UF CAPACITOR, ELECT.
C2,3 220UF CAPACITOR, ELECT.
C7,C8,C27,C28 22PF CAPACITOR, CER. DISK
J4 34 VSC CONNECTORS
R0,R2-5 10K,1/8W,5% RESISTORS
R1 10M,1/8W,5% RESISTORS
R6 4.7K,1/4W,1% RESISTORS
R7 10K TRIM-POT
D1,D2 1N4148
DIODE
Q1 VPO300M FET
VR1 LM7805 REGULATOR
BR1 VMO8 RECTIFIER
J3 3 PIN TERM. BLOCK
Y1 8MHz XTAL, LOW PROFILE
Y2 3.6864MHz XTAL.
LVI1 8054 IC
U5,U7 74HC00 IC
U8 74HC138 IC
U9 74HC373 IC
U1 F68HC11 IC
U14 74HC27 IC
U12 74HC133 IC
U13 MM74C923 IC
U6,U16 MAX232 IC
U10,U11 75176 IC
U18,U19
U2 KM6264BL-10 IC
U17 75C1406 IC
U15 R65C51P2
IC
U10,U11 8 PIN SOCKET
U18,U19
U5,U7,U14 14 PIN SOCKET
U6,U8,U12,U16 16 PIN SOCKET
U17
U9,U13 20 PIN SOCKET
U2,U3,U4,U15 28 PIN SOCKET
U1 52 PIN SOCKET
J4 34 VSC SPACER
SHUNTS
J7 1x9 HEADER PINS
J6 1x14 HEADER PINS
J8 1x2 HEADER PINS
J1,C 2x8 HEADER PINS
A,B,D,E,F,G,K 1X3 HEADER PINS
AA,BB,CC
SHUNTS
N,O,P 2x6 HEADER PINS
SHUNTS
H,I,J 1X2 2-PIN SOCKET
J9,J10 2X5 HEADER PINS
J5 2X17
HEADER PINS
J2 2-PIN TERM. BLOCK
JP17 16-pin header PIN 9to13
PIN 14to15
JP16 16-pin header PIN 9to10
NMIX-0020-S1 PCB
APPLICATION
NOTE
INTEL
FORMAT DUMP COMMAND
The
following Forth program allows a section of memory to be
dumped
out the serial channel in the Intel hex format which is a
standard
used by many of the commercially available PROM
programmers.
This program should allow the use of such
programmers
to capture programs and data in EPROMs, which are
not
supported for programming by the NMIX-0026 directly.
HEX
VARIABLE
CHKSUM
: CE
DUP A < IF 30 ELSE 37 THEN + EMIT ; ( CONVERT AND EMIT )
: 2.R
FF AND 10 /MOD CE CE ;
: 4.R 0
100 UM/MOD 2.R 2.R ;
:
INTEL-DUMP ( addr count --- )
OVER + SWAP ( CONVERTS ADDR & COUNT TO
UPPER, LOWER ADDR )
BEGIN
CR
2DUP 20 + MIN ( MAKE NEXT LINE OF OUTPUT
UP TO 32 BYTES LONG)
SWAP ( BRING UP START ADDRESS, MOVE DOWN
END ADDRESS )
." :" ( BEGIN THE RECORD )
2DUP - ( FIND OUT # OF BYTES IN THIS
RECORD )
DUP CHKSUM ! ( BEGIN CHKSUM COMPUTATION )
2.R ( PRINT # OF BYTES IN RECORD IN TWO
DIGIT FIELD )
DUP 100 /MOD + CHKSUM +! ( ADD START
ADDRESS TO CHKSUM )
DUP 4.R ( PRINT START ADDRESS IN FOUR
DIGIT FIELD )
." 00" ( PRINT RECORD TYPE, NO
NEED TO ADD TO CHKSUM )
>R DUP R> ( MAKE START STOP #S FOR
DO LOOP )
DO
I C@ 2.R ( PRINT HEX BYTE IN TWO DIGIT
FIELD )
I C@ CHKSUM +! ( UPDATE CHKSUM )
LOOP
CHKSUM @ FF AND NEGATE 2.R ( PRINT CHKSUM
NEG 2 DIGIT FIELD )
2DUP =
UNTIL ( KEEP GOING TILL LINE END IS = TO
BLOCK END )
CR ." :00000001FF" CR ( TACK ON
END RECORD )
2DROP
;