\ Count for 1 msec at 5 MHz timer clock DECIMAL 5000 CONSTANT TMRD2_COUNT EEWORD HEX 0C00 CONSTANT IOBASE EEWORD \ use 1000 for ServoPod \ Timer D2 registers IOBASE 0170 + CONSTANT TMRD2_CMP1 EEWORD IOBASE 0173 + CONSTANT TMRD2_LOAD EEWORD IOBASE 0176 + CONSTANT TMRD2_CTRL EEWORD IOBASE 0177 + CONSTANT TMRD2_SCR EEWORD \ GPIO interrupt control register FFFB CONSTANT GPIO_IPR EEWORD 2000 CONSTANT GPIO_IPL_2 EEWORD \ bit which enables Channel 2 IPL \ Interrupt vector & control. \ Timer D channel 2 is vector 36, IRQ table address $48 0040 7D80 + CONSTANT TMRD2_VECTOR EEWORD \ Timer D channel 2 is controlled by Group Priority Register GPR8, bits 2:0 \ Timer will use interrupt priority channel 2 IOBASE 0268 + CONSTANT TMRD2_GPR EEWORD 0007 CONSTANT TMRD2_PLR_MASK EEWORD 0003 CONSTANT TMRD2_PLR_PRIORITY EEWORD \ pri’ty channel 2 in bits 2:0 \ Initialize Timer D2 : START-TMRD2 \ Set compare 1 register to desired # of cycles TMRD2_COUNT TMRD2_CMP1 ! \ Set reload register to zero 0 TMRD2_LOAD ! \ Timer control register \ 001 = normal count mode \ 1 011 = IPbus clock / 8 = 5 MHz timer clock \ 0 0 = secondary count source n/a \ 0 = count repeatedly \ 1 = count until compare, then reinit \ 0 = count up \ 0 = no co-channel init \ 000 = OFLAG n/a \ 0011 0110 0010 0000 = $3620 3620 TMRD2_CTRL ! \ Timer status & control register \ Clear TCF flag, set interrupt enable flag 8000 TMRD2_SCR CLEAR-BITS 4000 TMRD2_SCR SET-BITS \ Interrupt Controller \ set the interrupt channel = 3 for Timer D3 TMRD2_PLR_MASK TMRD2_GPR CLEAR-BITS TMRD2_PLR_PRIORITY TMRD2_GPR SET-BITS \ enable that interrupt channel in processor status register GPIO_IPL_2 GPIO_IPR SET-BITS ; EEWORD \ Stop Timer D2 : STOP-TMRD2 \ Timer control register \ 000x xxxx xxxx xxxx = no count E000 TMRD2_CTRL CLEAR-BITS \ Timer status & control register \ Clear TCF flag, clear interrupt enable flag C000 TMRD2_SCR CLEAR-BITS ; EEWORD VARIABLE TICKS EEWORD \ High level word to handle the timer D2 interrupt : TMRD2-IRPT \ clear the TCF flag to clear the interrupt 8000 TMRD2_SCR CLEAR-BITS \ increment the ticks counter 1 TICKS +! ; EEWORD HEX 0041 CONSTANT WP EEWORD CODE-SUB INT-SERVICE DE0B P, \ LEA (SP)+ D00B P, \ MOVE X0,X:(SP)+ D10B P, \ MOVE Y0,X:(SP)+ D30B P, \ MOVE Y1,X:(SP)+ D08B P, \ MOVE A0,X:(SP)+ D60B P, \ MOVE A1,X:(SP)+ D28B P, \ MOVE A2,X:(SP)+ D18B P, \ MOVE B0,X:(SP)+ D70B P, \ MOVE B1,X:(SP)+ D38B P, \ MOVE B2,X:(SP)+ D80B P, \ MOVE R0,X:(SP)+ D90B P, \ MOVE R1,X:(SP)+ DA0B P, \ MOVE R2,X:(SP)+ DB0B P, \ MOVE R3,X:(SP)+ DD0B P, \ MOVE N,X:(SP)+ DE8B P, \ MOVE LC,X:(SP)+ DF8B P, \ MOVE LA,X:(SP)+ F854 P, OBJREF P, \ MOVE X:OBJREF,R0 FA54 P, WP P, \ MOVE X:WP,R2 D80B P, \ MOVE R0,X:(SP)+ DA1F P, \ MOVE R2,X:(SP) ; Note no increment on last push! 87D0 P, ' TMRD2-IRPT CFA P, \ MOVE #$XXXX,R0 ; CFA of the word to execute E9C8 P, ATO4 P, \ JSR ATO4 ; do that Forth word FA1B P, \ MOVE X:(SP)-,R2 ; restore the saved wp F81B P, \ MOVE X:(SP)-,R0 ; restore the saved objref FF9B P, \ MOVE X:(SP)-,LA DA54 P, WP P, \ MOVE R2,X:WP D854 P, OBJREF P, \ MOVE R0,X:OBJREF FE9B P, \ MOVE X:(SP)-,LC FD1B P, \ MOVE X:(SP)-,N FB1B P, \ MOVE X:(SP)-,R3 FA1B P, \ MOVE X:(SP)-,R2 F91B P, \ MOVE X:(SP)-,R1 F81B P, \ MOVE X:(SP)-,R0 F39B P, \ MOVE X:(SP)-,B2 F71B P, \ MOVE X:(SP)-,B1 F19B P, \ MOVE X:(SP)-,B0 F29B P, \ MOVE X:(SP)-,A2 F61B P, \ MOVE X:(SP)-,A1 F09B P, \ MOVE X:(SP)-,A0 F31B P, \ MOVE X:(SP)-,Y1 F11B P, \ MOVE X:(SP)-,Y0 F01B P, \ MOVE X:(SP)-,X0 EDD9 P, \ RTI END-CODE EEWORD \ Install the interrupt vector in Program Flash ROM E984 TMRD2_VECTOR PF! \ JMP instruction ' INT-SERVICE CFA 2+ TMRD2_VECTOR 1+ PF! \ target address